-
公开(公告)号：US09786719B2
公开(公告)日：2017-10-10
申请号：US13414329
申请日：2012-03-07
CPC分类号： H01L27/2436 , H01L27/101 , H01L27/2463 , H01L45/06 , H01L45/1233
摘要： Embodiments disclosed herein may relate to forming a base contact layout in a memory device.
-
公开(公告)号：US20140003114A1
公开(公告)日：2014-01-02
申请号：US13538880
申请日：2012-06-29
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C13/0004 , G11C2213/71 , G11C2213/77 , H01L27/0207 , H01L27/10 , H01L27/1052 , H01L27/2481 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit may include lines that traverse a cross-point array, the lines fabricated at a first pitch on a first layer, wherein the first pitch is sub-lithographic, and leads on a second layer, the leads having a second pitch that is twice as large as the first pitch. The lines may be routed outside of the array in alternating groups to opposite sides of the array where the lines couple to the leads.
摘要翻译： 集成电路可以包括穿过交叉点阵列的线，在第一层上以第一间距制造的线，其中第一间距是次光刻的，并且在第二层上引出，引线具有第二间距， 是第一音高的两倍。 线可以以交替的阵列布线到阵列的相对两侧，其中线耦合到引线。
-
公开(公告)号：US08885382B2
公开(公告)日：2014-11-11
申请号：US13538880
申请日：2012-06-29
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C13/0004 , G11C2213/71 , G11C2213/77 , H01L27/0207 , H01L27/10 , H01L27/1052 , H01L27/2481 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit may include lines that traverse a cross-point array, the lines fabricated at a first pitch on a first layer, wherein the first pitch is sub-lithographic, and leads on a second layer, the leads having a second pitch that is twice as large as the first pitch. The lines may be routed outside of the array in alternating groups to opposite sides of the array where the lines couple to the leads.
摘要翻译： 集成电路可以包括穿过交叉点阵列的线，在第一层上以第一间距制造的线，其中第一间距是次光刻的，并且在第二层上引出，引线具有第二间距， 是第一音高的两倍。 线可以以交替的阵列布线到阵列的相对两侧，其中线耦合到引线。
-
4.发明申请公开(公告)号：US20130235654A1
公开(公告)日：2013-09-12
申请号：US13414329
申请日：2012-03-07
CPC分类号： H01L27/2436 , H01L27/101 , H01L27/2463 , H01L45/06 , H01L45/1233
摘要： Embodiments disclosed herein may relate to forming a base contact layout in a memory device.
摘要翻译： 本文公开的实施例可涉及在存储器件中形成基底接触布局。
-
公开(公告)号：US20180366370A1
公开(公告)日：2018-12-20
申请号：US16111004
申请日：2018-08-23
IPC分类号： H01L21/768 , H01L45/00 , H01L27/24 , H01L23/522 , H01L21/033 , H01L21/311
摘要： Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one dimension with a more relaxed pitch. Buried hard mask materials permit self-alignment of the lines and contacts without a critical mask, such as for word-line electrode lines and word-line contacts in a memory device.
-
公开(公告)号：US09269747B2
公开(公告)日：2016-02-23
申请号：US13593065
申请日：2012-08-23
IPC分类号： H01L27/24 , H01L45/00 , H01L21/768 , H01L21/033 , H01L21/311
CPC分类号： H01L21/76897 , H01L21/0337 , H01L21/31144 , H01L21/7681 , H01L21/76816 , H01L23/5226 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/065 , H01L45/1233 , H01L45/126 , H01L45/16 , H01L45/1675 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one dimension with a more relaxed pitch. Buried hard mask materials permit self-alignment of the lines and contacts without a critical mask, such as for word-line electrode lines and word-line contacts in a memory device.
摘要翻译： 方法和结构提供了从它们延伸的细间距和自对准触点的水平导线，其中触点具有至少一个具有更宽松间距的尺寸。 掩埋硬掩模材料允许线和触点的自对准，而不需要临界掩模，例如用于存储器件中的字线电极线和字线接触。
-
公开(公告)号：US20130193398A1
公开(公告)日：2013-08-01
申请号：US13358882
申请日：2012-01-26
申请人： Fabio Pellizzer , Antonino Rigano
发明人： Fabio Pellizzer , Antonino Rigano
CPC分类号： H01L45/122 , H01L27/2427 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675 , H01L45/1691
摘要： Memory arrays and methods of forming the same are provided. One example method of forming a memory array can include forming a first conductive material having a looped feature using a self-aligning multiple patterning technique, and forming a first sealing material over the looped feature. A first chop mask material is formed over the first sealing material. The looped feature and the first sealing material are removed outside the first chop mask material.
摘要翻译： 提供了存储器阵列及其形成方法。 形成存储器阵列的一个示例性方法可以包括使用自对准多图案化技术形成具有环形特征的第一导电材料，以及在环形特征上形成第一密封材料。 在第一密封材料上方形成第一剁掩模材料。 环状特征和第一密封材料在第一剁掩模材料外移除。
-
公开(公告)号：US09525007B2
公开(公告)日：2016-12-20
申请号：US12979461
申请日：2010-12-28
申请人： Fabio Pellizzer , Antonino Rigano
发明人： Fabio Pellizzer , Antonino Rigano
CPC分类号： H01L27/2463 , G11C13/0004 , H01L27/0207 , H01L45/06 , H01L45/1233 , H01L45/16
摘要： A phase change memory device with reduced programming disturbance and its operation are described. The phase change memory includes an array with word lines and bit lines and voltage controlling elements coupled to bit lines adjacent to an addressed bit line to maintain the voltage of the adjacent bit lines within an allowed range.
摘要翻译： 描述了具有减少的编程干扰及其操作的相变存储器件。 相变存储器包括具有字线和位线的阵列和耦合到与寻址位线相邻的位线的电压控制元件，以将相邻位线的电压维持在允许的范围内。
-
公开(公告)号：US08728940B2
公开(公告)日：2014-05-20
申请号：US13358882
申请日：2012-01-26
申请人： Fabio Pellizzer , Antonino Rigano
发明人： Fabio Pellizzer , Antonino Rigano
IPC分类号： H01L21/302
CPC分类号： H01L45/122 , H01L27/2427 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675 , H01L45/1691
摘要： Memory arrays and methods of forming the same are provided. One example method of forming a memory array can include forming a first conductive material having a looped feature using a self-aligning multiple patterning technique, and forming a first sealing material over the looped feature. A first chop mask material is formed over the first sealing material. The looped feature and the first sealing material are removed outside the first chop mask material.
摘要翻译： 提供了存储器阵列及其形成方法。 形成存储器阵列的一个示例性方法可以包括使用自对准多图案化技术形成具有环形特征的第一导电材料，以及在环形特征上形成第一密封材料。 在第一密封材料上方形成第一剁掩模材料。 环状特征和第一密封材料在第一剁掩模材料外移除。
-
公开(公告)号：US20140054534A1
公开(公告)日：2014-02-27
申请号：US13593065
申请日：2012-08-23
IPC分类号： H01L21/768 , H01L23/48 , H01L45/00
CPC分类号： H01L21/76897 , H01L21/0337 , H01L21/31144 , H01L21/7681 , H01L21/76816 , H01L23/5226 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/065 , H01L45/1233 , H01L45/126 , H01L45/16 , H01L45/1675 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one dimension with a more relaxed pitch. Buried hard mask materials permit self-alignment of the lines and contacts without a critical mask, such as for word-line electrode lines and word-line contacts in a memory device.
摘要翻译： 方法和结构提供了从它们延伸的细间距和自对准触点的水平导线，其中触点具有至少一个具有更宽松间距的尺寸。 掩埋硬掩模材料允许线和触点的自对准，而不需要临界掩模，例如用于存储器件中的字线电极线和字线接触。
-
-
-
-
-
-
-
-
-
搜索结果
11 条记录 (耗时 0.023 秒)
