公开(公告)号：US09406751B2

公开(公告)日：2016-08-02

申请号：US14296818

申请日：2014-06-05

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L29/08 ,  H01L27/12 ,  H01L29/786 ,  H01L21/84 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/786 ,  H01L29/78684

Abstract: A method for making a semiconductor device is provided. Raised source and drain regions are formed with a tensile strain-inducing material, after thermal treatment to form source drain extension regions, to thereby preserve the strain-inducing material in desired substitutional states.

Abstract translation: 提供一种制造半导体器件的方法。 在热处理之后，用拉伸应变诱导材料形成凸起的源极和漏极区域以形成源极漏极延伸区域，从而将应变诱导材料保持在期望的替代状态。

公开(公告)号：US09390939B2

公开(公告)日：2016-07-12

申请号：US14289737

申请日：2014-05-29

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/51 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/66 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L23/535 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/285 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5283 ,  H01L23/53266 ,  H01L29/6659 ,  H01L29/66643 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method disclosed includes, among other things, conformably depositing a layer of contact insulating material and a conductive material layer in a contact opening, forming a reduced-thickness sacrificial material layer in the contact opening so as to expose a portion, but not all, of the conductive material layer, removing portions of the conductive material layer and the layer of contact insulating material positioned above the upper surface of the reduced-thickness sacrificial material layer, removing the reduced-thickness sacrificial material layer, and forming a conductive contact in the contact opening that contacts the recessed portions of the conductive material layer and the layer of contact insulating material.

Abstract translation: 所公开的一种方法包括在接触开口中顺应地沉积接触绝缘材料层和导电材料层，在接触开口中形成减小厚度的牺牲材料层，以暴露部分，但不是全部， 的导电材料层的去除部分，去除部分导电材料层和接触绝缘材料层位于减薄厚度的牺牲材料层的上表面之上，去除减薄的牺牲材料层，并在其中形成导电接触 接触开口，其接触导电材料层的凹部和接触绝缘材料层。

公开(公告)号：US20160181381A1

公开(公告)日：2016-06-23

申请号：US14577431

申请日：2014-12-19

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GlobalFoundries Inc

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/41783 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A FinFET device includes a semiconductor fin, a gate electrode extending over a channel of the fin and sidewall spacers on each side of the gate electrode. A dielectric material is positioned on each side of a bottom portion of said fin, with an oxide material on each side of the fin overlying the dielectric material. A recessed region, formed in the fin on each side of the channel region, is delimited by the oxide material. A raised source region fills the recessed region and extends from the fin on a first side of the gate electrode to cover the oxide material to a height which is in contact with the sidewall spacer. A raised drain region fills the recessed region and extends from the fin on a second side of the gate electrode to cover the oxide material to a height which is in contact with the sidewall spacer.

Abstract translation: FinFET器件包括半导体鳍片，在鳍片的沟道上延伸的栅极电极和在栅电极的每一侧上的侧壁间隔物。 电介质材料位于所述散热片的底部的每一侧上，其中在散热片的每侧的氧化物材料覆盖在电介质材料上。 在通道区域的每一侧的翅片上形成的凹陷区域由氧化物材料界定。 凸起的源极区域填充凹陷区域并且在栅电极的第一侧上从翅片延伸以将氧化物材料覆盖到与侧壁间隔物接触的高度。 凸起的漏极区域填充凹陷区域并且在栅电极的第二侧上从翅片延伸以将氧化物材料覆盖到与侧壁间隔物接触的高度。

公开(公告)号：US20160163850A1

公开(公告)日：2016-06-09

申请号：US14560255

申请日：2014-12-04

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GlobalFoundries Inc

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh ,  Xiuyu Cai

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L27/092 ,  H01L29/08

CPC classification number: H01L29/785 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/41758 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7848

Abstract: A FinFET transistor includes a fin of semiconductor material with a transistor gate electrode extending over a channel region. Raised source and drain regions of first epitaxial growth material extending from the fin on either side of the transistor gate electrode. Source and drain contact openings extend through a pre-metallization dielectric material to reach the raised source and drain regions. Source and drain contact regions of second epitaxial growth material extend from the first epitaxial growth material at the bottom of the source and drain contact openings. A metal material fills the source and drain contact openings to form source and drain contacts, respectively, with the source and drain contact regions. The drain contact region may be offset from the transistor gate electrode by an offset distance sufficient to provide a laterally diffused metal oxide semiconductor (LDMOS) configuration within the raised source region of first epitaxial growth material.

Abstract translation: FinFET晶体管包括具有在沟道区域上延伸的晶体管栅电极的半导体材料的鳍。 从晶体管栅电极的两侧的鳍延伸的第一外延生长材料的引出源区和漏区。 源极和漏极接触开口延伸穿过预金属化电介质材料以到达升高的源极和漏极区域。 第二外延生长材料的源极和漏极接触区域在源极和漏极接触开口的底部处从第一外延生长材料延伸。 金属材料填充源极和漏极接触开口，以分别与源极和漏极接触区域形成源极和漏极接触。 漏极接触区域可以从晶体管栅电极偏移足以在第一外延生长材料的升高的源极区域内提供横向扩散的金属氧化物半导体（LDMOS）配置的偏移距离。

公开(公告)号：US09337050B1

公开(公告)日：2016-05-10

申请号：US14675045

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/8234

CPC classification number: H01L21/3086 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211

Abstract: One illustrative method disclosed herein includes, among other things, forming an inverted, generally T-shaped mandrel feature having a base mandrel structure and a substantially vertically oriented fin mandrel structure, the base mandrel structure having a lateral width that is greater than a lateral width of the fin mandrel structure, forming a sidewall spacer adjacent the sidewalls of the base mandrel structure and the fin mandrel structure, performing at least one etching process to remove portions of the inverted, generally T-shaped mandrel feature not covered by a sidewall spacer, wherein, after the etching process is completed, the sidewall spacers and remaining portions of the mandrel feature, collectively, define a fin pattern, and performing at least one additional process operation to form a plurality of fins in the substrate that correspond to the fin pattern.

Abstract translation: 本文公开的一种说明性方法包括形成具有基本心轴结构和基本垂直取向的翅片心轴结构的倒置的大体T形心轴特征，所述基部心轴结构具有大于横向宽度的横向宽度 形成翅片心轴结构的侧壁间隔件，邻近基部心轴结构和翅片心轴结构的侧壁形成侧壁间隔件，执行至少一个蚀刻工艺以去除未被侧壁间隔件覆盖的反向大体T形心轴特征的部分， 其中，在蚀刻工艺完成之后，所述侧壁间隔件和所述心轴特征的剩余部分共同地限定翅片图案，并执行至少一个附加工艺操作以在所述基板中形成对应于所述翅片图案的多个翅片 。

公开(公告)号：US20160035863A1

公开(公告)日：2016-02-04

申请号：US14883049

申请日：2015-10-14

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Ajey P. Jacob ,  Witold P. Maszara ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/66 ,  H01L29/165 ,  H01L21/02 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7849 ,  H01L29/785

Abstract: An illustrative method includes forming a FinFET device above structure comprising a semiconductor substrate, a first epi semiconductor material and a second epi semiconductor material that includes forming an initial fin structure that comprises portions of the semiconductor substrate, the first epi material and the second epi material, recessing a layer of insulating material such that a portion, but not all, of the second epi material portion of the initial fin structure is exposed so as to define a final fin structure, forming a gate structure above and around the final fin structure, removing the first epi material of the initial fin structure and thereby define an under-fin cavity under the final fin structure and substantially filling the under-fin cavity with a stressed material.

Abstract translation: 一种说明性的方法包括在包括半导体衬底，第一外延半导体材料和第二外延半导体材料的结构之上形成FinFET器件，其包括形成包括半导体衬底，第一外延材料和第二外延材料的部分的初始鳍结构 使一层绝缘材料凹陷，使得初始翅片结构的第二外延材料部分的一部分（但不是全部）暴露以便限定最终的翅片结构，在最后的翅片结构的上方和周围形成栅极结构， 去除初始翅片结构的第一外延材料，从而在最终翅片结构下限定底鳍腔，并用应力材料基本上填充底鳍腔。

公开(公告)号：US20150380258A1

公开(公告)日：2015-12-31

申请号：US14314384

申请日：2014-06-25

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Chun-chen Yeh ,  Kejia Wang

IPC: H01L21/308 ,  H01L29/205 ,  H01L29/78

CPC classification number: H01L29/205 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods and structures for forming fin structures whilst controlling the height of the fin structures with high uniformity across large areas are described. According to some aspects, a multi-layer structure comprising a first etch-stop layer and a second etch-stop layer separated from a substrate and from each other by spacer layers is formed on a substrate. Trenches may be formed through the first and second etch-stop layers. A buffer layer may be formed in the trenches, filling the trenches to a level approximately at a position of the first etch-stop layer. A semiconductor layer may be formed above the buffer layer and etched back to the second etch-stop layer to form semiconductor fins of highly uniform heights.

Abstract translation: 描述了形成翅片结构的方法和结构，同时在大面积上以高均匀性控制翅片结构的高度。 根据一些方面，在衬底上形成包括由衬底分离并通过间隔层彼此分离的第一蚀刻停止层和第二蚀刻停止层的多层结构。 沟槽可以通过第一和第二蚀刻停止层形成。 可以在沟槽中形成缓冲层，将沟槽填充到大致在第一蚀刻停止层的位置处的水平。 半导体层可以形成在缓冲层的上方并被回蚀刻到第二蚀刻停止层以形成高均匀高度的半导体鳍片。

公开(公告)号：US20150372104A1

公开(公告)日：2015-12-24

申请号：US14312418

申请日：2014-06-23

Applicant: STMICROELCTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh ,  Xiuyu Cai

IPC: H01L29/423 ,  H01L29/16 ,  H01L29/06 ,  H01L29/51 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/10 ,  H01L29/161 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78696

Abstract: A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wrap-around gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.

Abstract translation: 描述了一种高性能GAA FET，其中垂直堆叠的硅纳米线在传统的FinFET晶体管中承载与鳍片基本上相同的驱动电流，但是在较低的工作电压下并且具有更高的可靠性。 在现有的纳米线GAA FET中出现的一个问题是，当使用金属来形成环绕栅极时，在源极和漏极区域之间以及在通道下方的金属栅极部分可以产生短路。 然而，本文所述的垂直堆叠的纳米线器件在形成栅极之前通过形成与源极和漏极区域接触的绝缘屏障来避免这种短路。 通过使用牺牲膜，制造工艺几乎完全自对准，使得仅需要一个光刻掩模层，这显着降低制造成本。

公开(公告)号：US09202920B1

公开(公告)日：2015-12-01

申请号：US14447727

申请日：2014-07-31

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Chun-chen Yeh ,  Ruilong Xie ,  Xiuyu Cai

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848

Abstract: Methods and structures for forming short-channel finFETs with vertical and abrupt source and drain junctions are described. During fabrication, source and drain regions of the finFET may be recessed vertically and laterally under gate spacers. A buffer having a high dopant density may be formed on vertical sidewalls of the channel region after recessing the fin. Raised source and drain structures may be formed at the recessed source and drain regions. The raised source and drain structures may impart strain to the channel region.

Abstract translation: 描述了用于形成具有垂直和突然的源极和漏极结的短沟道finFET的方法和结构。 在制造期间，finFET的源极和漏极区域可以在栅极间隔物下方垂直和横向地凹陷。 具有高掺杂浓度的缓冲器可以在凹陷鳍片之后形成在沟道区域的垂直侧壁上。 可以在凹陷的源极和漏极区域形成升高的源极和漏极结构。 升高的源极和漏极结构可能对沟道区域施加应变。

公开(公告)号：US09184162B2

公开(公告)日：2015-11-10

申请号：US14615762

申请日：2015-02-06

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Murat Kerem Akarvardar ,  Xiuyu Cai ,  Ajey Poovannummoottil Jacob

IPC: H01L27/12 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/76208 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/0653

Abstract: Fin field effect transistor integrated circuits and methods for producing the same are provided. A fin field effect transistor integrated circuit includes a plurality of fins extending from a semiconductor substrate. Each of the plurality of fins includes a fin sidewall, and each of the plurality of fins extends to a fin height such that a trough with a trough base is defined between adjacent fins. A second dielectric is positioned within the trough, where the second dielectric directly contacts the semiconductor substrate at the trough base. The second dielectric extends to a second dielectric height less than the fin height such that protruding fin portions extend above the second dielectric. A first dielectric is positioned between the fin sidewall and the second dielectric.

Abstract translation: 提供了Fin场效应晶体管集成电路及其制造方法。 翅片场效应晶体管集成电路包括从半导体衬底延伸的多个鳍。 多个翅片中的每一个包括翅片侧壁，并且多个翅片中的每一个延伸到翅片高度，使得具有槽底部的凹槽限定在相邻翅片之间。 第二电介质位于槽内，其中第二电介质在槽底部直接接触半导体衬底。 第二电介质延伸到小于翅片高度的第二介电高度，使得突出的翅片部分在第二电介质上方延伸。 第一电介质位于翅片侧壁和第二电介质之间。