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218 条记录 (耗时 0.032 秒)

    Screw member with elastically deformable features
    124.
    发明授权
    Screw member with elastically deformable features 失效
    具有弹性变形特征的螺杆构件

    公开(公告)号：US06514025B2

    公开(公告)日：2003-02-04

    申请号：US09862073

    申请日：2001-05-21

    申请人： Tetsuya Watanabe

    发明人： Tetsuya Watanabe

    IPC分类号： F16B3930

    CPC分类号： F16B39/30 ,  F16B33/02 ,  F16B39/284

    摘要： A screw member having a loosening prevention function is provided to improve a fastening power and a relative strength in thread connection. With an arrangement to provide a first crest portion and a second crest portion at the opposite ends of a thread point, a first screw member generates a loosening prevention effect due to elastic deformation of the first crest portion and the second crest portion, with the entire thread flank from the base portion to the point brought into contact with a second screw member on the both surfaces of the thread flanks. With this arrangement, a strong fastening power can be obtained, and a clamping force applied to the thread is distributed over the thread, thereby enabling improvement in the relative strength in thread connection.

    摘要翻译： 提供具有松动防止功能的螺纹构件以提高螺纹连接中的紧固力和相对强度。 通过在螺纹点的相对端设置第一顶部部分和第二顶部部分的布置，第一螺纹部件由于第一顶部部分和第二顶部部分的弹性变形而产生松动防止效果，整个 螺纹齿从基部到与螺纹面的两个表面上的第二螺纹构件接触的点。 通过这种布置，可以获得强大的紧固力，并且施加到螺纹的夹紧力分布在螺纹上，从而可以提高螺纹连接中的相对强度。

    Semiconductor memory device permitting time required for writing data to be reduced
    125.
    发明授权
    Semiconductor memory device permitting time required for writing data to be reduced 失效
    允许减少写入数据所需的时间的半导体存储器件

    公开(公告)号：US06201758B1

    公开(公告)日：2001-03-13

    申请号：US09499044

    申请日：2000-02-07

    申请人： Chikayoshi Morishima ,  Yasunobu Nakase ,  Tetsuya Watanabe ,  Niichi Itoh

    发明人： Chikayoshi Morishima ,  Yasunobu Nakase ,  Tetsuya Watanabe ,  Niichi Itoh

    IPC分类号： G11C800

    CPC分类号： G11C11/419

    摘要： A precharge circuit and a bit line load circuit are provided to a read bit line pair. The bit line load circuit continuously supplies a prescribed current to a read bit line. When data is written to one of memory cells selected in common by one read word line, the level of each read bit line will not be lowered to the level of the ground potential by the bit line load circuit if a read word line is activated, and therefore the loads of both discharge and charge operations by transistors in the memory cell are reduced.

    摘要翻译： 向读位线对提供预充电电路和位线负载电路。 位线负载电路将规定的电流连续地提供给读位线。 当将数据写入一个读取字线共同选择的存储器单元之一时，如果读取的字线被激活，则每个读取位线的电平将不会被位线负载电路降低到地电位的电平， 因此减小存储单元中的晶体管的放电和充电操作的负载。

    Cache memory with plurality of congruence sets and sense amplifiers shared among the congruence sets
    126.
    发明授权
    Cache memory with plurality of congruence sets and sense amplifiers shared among the congruence sets 失效
    具有多个等同集和高斯集合之间共享的读出放大器的高速缓冲存储器

    公开(公告)号：US5522056A

    公开(公告)日：1996-05-28

    申请号：US101800

    申请日：1993-08-03

    申请人： Tetsuya Watanabe ,  Akira Yamada

    发明人： Tetsuya Watanabe ,  Akira Yamada

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/0864

    摘要： A cache memory with a data memory divided into a plurality of word arrays, each of which is selectable by a word select indicator. Each word array is further divided into a plurality of bit arrays, each of which correspond to a bit of a word, and include congruence set memories for each congruence set. A bit array is connected to a sense amplifier via a congruence set selector, thereby one set of congruence set memories of the word arrays in the data memory is selected, and one congruence set memory is selected from each of the bit arrays by a congruence set selector to be connected with a sense amplifier, so that only one sense amplifier has to be provided for each bit in each word in an entry of the data memory, thus eliminating the need to increase the number sense amplifiers as the number of congruence sets increases. Furthermore, as only the sense amplifier associated with the selected word array is operational, current consumption is reduced.

    摘要翻译： 一种具有数据存储器的高速缓存存储器，被划分为多个字阵列，每个字阵列可由字选择指示器选择。 每个字阵列进一步被划分成多个位阵列，每个位阵列对应一个字的位，并且包括每个一致集合的一致集合存储器。 一个位阵列通过一个一致的集合选择器连接到一个读出放大器，从而选择数据存储器中的字阵列的一组一致的集合存储器，并且通过一致集合从每个位阵列中选择一个一致集合存储器 选择器与读出放大器连接，从而必须为数据存储器的条目中的每个字中的每个位提供一个读出放大器，从而不再需要增加数量检测放大器，因为一致性集合的数量增加 。 此外，由于只有与所选字阵列相关联的读出放大器可操作，所以消耗电流。

    Operand address calculation in a pipeline processor by decomposing the operand specifier into sequential step codes
    127.
    发明授权
    Operand address calculation in a pipeline processor by decomposing the operand specifier into sequential step codes 失效
    通过将操作指定器分解为顺序步骤代码，在管道处理器中进行操作地址计算

    公开(公告)号：US5129068A

    公开(公告)日：1992-07-07

    申请号：US313650

    申请日：1989-02-21

    申请人： Tetsuya Watanabe ,  Toyohiko Yoshida

    发明人： Tetsuya Watanabe ,  Toyohiko Yoshida

    IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/32 ,  G06F9/35 ,  G06F9/355

    CPC分类号： G06F9/355 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/35

    摘要： A pipeline data processor includes an instruction fetch unit, an instruction decoding unit, an address calculation unit, an operand fetch unit and an instruction operation execution unit. After an instruction, or a part of an instruction, is sent from the instruction fetch unit to the decoding unit, the decoding unit decodes at least a portion of the instruction. For some instructions, the decoding unit outputs two or more step codes to achieve processing of a single operand address. In one embodiment, the operand specifier of the instruction includes a base value and at least one address extension field. The decoding unit outputs a first step code based on the base value and, subsequently, a second step code based on the address extension field. In another embodiment, an operand specifier can include up to an arbitrary number of address extension fields. The decoding unit outputs a step code corresponding to the base value of the address and another step code for each of the plurality of address extension fields. The address calculation unit sequentially receives the plurality of step codes which relate to a single operand and, when address calculation of the operand is completed, sends the result as a fuuther step code to the operand fetch unit.

    Vibratory transducer
    129.
    发明授权
    Vibratory transducer 失效
    振动传感器

    公开(公告)号：US4841775A

    公开(公告)日：1989-06-27

    申请号：US145156

    申请日：1988-01-19

    申请人： Kyoichi Ikeda ,  Tetsuya Watanabe ,  Yasushi Higashino

    发明人： Kyoichi Ikeda ,  Tetsuya Watanabe ,  Yasushi Higashino

    IPC分类号： G01D5/243 ,  G01L1/10 ,  G01L1/16 ,  G01L1/18 ,  G01L9/00 ,  G01N9/00 ,  G01N35/00 ,  G01P15/08 ,  G01P15/097 ,  G01P15/10 ,  H01L21/60 ,  H04R17/08

    CPC分类号： H01L21/76897 ,  G01D5/243 ,  G01L1/162 ,  G01L1/183 ,  G01L1/186 ,  G01L9/0019 ,  G01L9/002 ,  G01L9/0022 ,  G01L9/0023 ,  G01N9/002 ,  G01P15/0802 ,  G01P15/097 ,  G01N2035/00237 ,  H01L2924/3011 ,  H04R17/08

    摘要： A vibratory transducer comprising a vibratory beam composed of an n-type layer and having at least one end fixed. The vibratory beam is formed by selectively etching an n-type layer formed by adding impurities locally to a single silicon crystal. The vibratory transducer also comprises means for vibrating the vibratory beam and means for detecting vibration of the vibratory beam. The vibratory transducer measures pressure, temperature, density, etc, by detecting change in the resonant frequency of the vibratory beam. The vibratory beam can be finely etched irrespective of the density of the impurities therein by forming the vibratory beam in an alkaline aqueous solution while applying a negative DC or pulsed voltage to a p-type layer and a positive DC or pulsed voltage to an n-type layer. The vibrating and detecting means for the vibratory beam can be easily provided by making a diode and a transistor including the vibratory beam in the transducer.

    摘要翻译： 一种振动换能器，包括由n型层组成并且至少一端固定的振动梁。 通过选择性地蚀刻通过将杂质局部添加到单个硅晶体而形成的n型层来形成振动束。 振动换能器还包括用于振动振动梁的装置和用于检测振动梁的振动的装置。 振动传感器通过检测振动梁的共振频率的变化来测量压力，温度，密度等。 通过在碱性水溶液中形成振动束，同时向p型层施加负的DC或脉冲电压，并向正极直流或脉冲电压施加负的DC或脉冲电压，可以精细地蚀刻振动束，而不管其中的杂质的密度如何。 类型层。 用于振动束的振动和检测装置可以通过在换能器中制造包括振动束的二极管和晶体管来容易地提供。

    Insole
    130.
    发明授权
    Insole 失效
    鞋垫

    公开(公告)号：US4510699A

    公开(公告)日：1985-04-16

    申请号：US437300

    申请日：1982-10-28

    申请人： Toshiro Nakamura ,  Tetsuya Watanabe

    发明人： Toshiro Nakamura ,  Tetsuya Watanabe

    IPC分类号： A61F5/14 ,  A43B13/40 ,  A43B13/38

    CPC分类号： A61F5/14

    摘要： An insole the material for which is made from a elastomer showing gum-like elasticity under the normal temperature, and which is provided with a wedge-shaped profile, irregularities, curves, and the like for the purpose of making the sole incline or correcting the state of unevenness thereof. It is used by being inserted inside shoes, slippers, sandals, etc., or by being worn on the sole of the foot with the aid of socks, simple holders or band bodies being molded integrally with the holders. Further, it may be made by utilizing a foam-formed body, or by boring small holes for air permeation therein for retaining warmth or making it light-weight.

    摘要翻译： 在常温下由弹性体形成的胶状弹性材料制成的鞋垫，为了使鞋底倾斜或矫正，设置有楔形轮廓，凹凸，曲线等。 不均匀状态。 通过插入鞋子，拖鞋，凉鞋等中，或者通过袜子，简单的保持器或带体与支架一体地模制而被佩戴在脚底上。 此外，可以通过利用泡沫成形体或通过钻孔来使其中的空气渗透以保持温暖或使其重量轻。