公开(公告)号：US10971362B2

公开(公告)日：2021-04-06

申请号：US16287107

申请日：2019-02-27

Applicant: International Business Machines Corporation

Inventor： Chanro Park ,  Ruilong Xie ,  Kangguo Cheng ,  Choonghyun Lee

IPC: H01L21/033 ,  H01L21/027 ,  G03F7/20 ,  H01L21/308

Abstract: A photolithography patterning stack and method for forming the same. The stack includes a plurality of patterned silicon oxide lines. A plurality of patterned silicon germanium lines each underlie and contact one patterned silicon oxide line of the plurality of patterned silicon oxide lines. The photolithography patterning stack further comprises a plurality of layers underlying the plurality of patterning silicon germanium lines. The method includes patterning at least a photoresist layer of a photolithographic patterning stack. The patterning exposing portions of a silicon germanium layer of the photolithographic patterning stack. A germanium oxide layer is formed in contact with the patterned photoresist layer and the portions of the silicon germanium layer. A plurality of silicon oxide layers is formed from the germanium oxide layer. Each of the silicon oxide layer is in contact with one of the portions of the silicon germanium layer.

公开(公告)号：US10930758B2

公开(公告)日：2021-02-23

申请号：US16102110

申请日：2018-08-13

Applicant: International Business Machines Corporation

Inventor： Shogo Mochizuki ,  Kangguo Cheng ,  Juntao Li ,  Choonghyun Lee

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L21/225 ,  H01L21/8238

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate. In the method, sacrificial spacer layers are formed on the plurality of fins, and portions of the semiconductor substrate located under the sacrificial spacer layers and located at sides of the plurality of fins are removed. Bottom source/drain regions are grown in at least part of an area where the portions of the semiconductor substrate were removed, and sacrificial epitaxial layers are grown on the bottom source/drain regions. The method also includes diffusing dopants from the bottom source/drain regions and the sacrificial epitaxial layers into portions of the semiconductor substrate under the plurality of fins. The sacrificial epitaxial layers are removed, and bottom spacers are formed in at least part of an area where the sacrificial epitaxial layers were removed.

公开(公告)号：US10916659B2

公开(公告)日：2021-02-09

申请号：US16134543

申请日：2018-09-18

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Choonghyun Lee ,  Pouya Hashemi ,  Takashi Ando ,  Jingyun Zhang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L29/08 ,  H01L21/308 ,  H01L29/10

Abstract: A FinFET having an asymmetric threshold voltage distribution is provided by forming a halo ion implantation region in a semiconductor fin, and in close proximity to a source region, of the FinFET. The halo ion implantation region is self-aligned to an outermost sidewall surface of the functional gate structure of the FinFET and it has a higher dopant concentration than the remaining portion of the channel region.

公开(公告)号：US10916638B2

公开(公告)日：2021-02-09

申请号：US16134526

申请日：2018-09-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Shogo Mochizuki ,  Choonghyun Lee ,  Juntao Li

IPC: H01L21/225 ,  H01L21/324 ,  H01L21/82 ,  H01L21/28 ,  H01L29/66 ,  H01L21/768 ,  H01L23/535 ,  H01L29/08 ,  H01L29/78

Abstract: A method of forming a fin field effect device is provided. The method includes forming one or more vertical fins on a substrate and a fin template on each of the vertical fins. The method further includes forming a gate structure on at least one of the vertical fins, and a top spacer layer on the at least one gate structure, wherein at least an upper portion of the at least one of the one or more vertical fins is exposed above the top spacer layer. The method further includes forming a top source/drain layer on the top spacer layer and the exposed upper portion of the at least one vertical fin. The method further includes forming a sacrificial spacer on opposite sides of the fin templates and the top spacer layer, and removing a portion of the top source/drain layer not covered by the sacrificial spacer to form a top source/drain electrically connected to the vertical fins.

公开(公告)号：US10903339B2

公开(公告)日：2021-01-26

申请号：US16679427

申请日：2019-11-11

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Kangguo Cheng ,  Juntao Li ,  Shogo Mochizuki

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/225 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/28

Abstract: Methods of fabrication and semiconductor structures includes vertical transport field effect transistors (VTFETs) including a top source/drain extension formed with a sacrificial doped layer. The sacrificial doped layer provides the doping source to form the extension and protects the top of the fin during fabrication so as to prevent thinning, among other advantages.

公开(公告)号：US10896962B2

公开(公告)日：2021-01-19

申请号：US16425165

申请日：2019-05-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Alexander Reznicek ,  Jingyun Zhang ,  Choonghyun Lee ,  Pouya Hashemi

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311

Abstract: Semiconductor devices and methods of forming the same include forming an inner spacer on a semiconductor fin. Two outer spacers are formed around the inner spacer, with one outer spacer being in contact with the inner spacer and with the other outer spacer being separated from the inner spacer by a gap. A dipole-forming layer is formed on the semiconductor fin in the gap. The inner spacer is etched away. A gate stack is formed on the semiconductor fin, between the outer spacers.

公开(公告)号：US20200381305A1

公开(公告)日：2020-12-03

申请号：US16425398

申请日：2019-05-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Jingyun Zhang ,  Choonghyun Lee ,  Pouya Hashemi

IPC: H01L21/8234 ,  H01L27/088

Abstract: Semiconductor devices and methods of forming the same include partially etching sacrificial layers in a first stack of alternating sacrificial layers and channel layers to form first recesses. A first inner spacer sub-layer is formed in the first recesses from a first dielectric material. A second inner spacer sub-layer is formed in the first recesses from a second dielectric material, different from the first dielectric material. The sacrificial layers are etched away. The first inner spacer sub-layer is etched away. A gate stack is formed on and around the channel layers and in contact with the second inner spacer sub-layer.

公开(公告)号：US20200373429A1

公开(公告)日：2020-11-26

申请号：US16420118

申请日：2019-05-22

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Takashi Ando ,  Alexander Reznicek ,  Jingyun Zhang ,  Pouya Hashemi

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L21/324 ,  H01L27/12 ,  H01L21/84

Abstract: A SiGe channel FinFET structure has an asymmetric threshold voltage, Vth, laterally along the SiGe channel. Uses of sacrificial layers, selective Ge condensation, and/or the use of spacers enable precise creation of first and second channel regions with different Ge concentration, even for channels with short lengths. The second channel region near the source side of the device is modified with a selective Germanium (Ge) condensation to have a higher Vth than the first channel region near the drain side. A lateral electric field is created in the channel to enhance carrier mobility.

公开(公告)号：US10833200B2

公开(公告)日：2020-11-10

申请号：US16738756

申请日：2020-01-09

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Kangguo Cheng ,  Juntao Li

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/84 ,  H01L29/49 ,  H01L21/3213 ,  H01L29/51 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/8234

Abstract: Techniques for reducing work function metal variability along the channel of VFET devices are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer; forming bottom source/drains at a base of the fins and bottom spacers on the bottom source/drains; forming gate stacks over the fins including a gate conductor having a combination of work function metals including an outer layer and at least one inner layer of the work function metals; isotropically etching the work function metals which recesses the gate stacks with an outwardly downward sloping profile; isotropically etching the at least one inner layer while covering the outer layer of the work function metals to eliminate the outwardly downward sloping profile of the gate stacks; forming top spacers above the gate stacks; and forming top source and drains at tops of the fins. A VTFET device is also provided.

公开(公告)号：US10833172B2

公开(公告)日：2020-11-10

申请号：US16104230

申请日：2018-08-17

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Christopher J. Waskiewicz ,  Miaomiao Wang ,  Hemanth Jagannathan

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/51 ,  H01L29/06 ,  H01L29/423 ,  H01L21/28 ,  H01L21/311 ,  H01L21/8238 ,  H01L29/08 ,  H01L21/265 ,  H01L21/3213

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin. A first source/drain contacts the semiconductor fin. An interfacial layer contacts sidewalls of the semiconductor fin. An insulating layer contacts the interfacial layer. One or more conductive gate layers encapsulate the interfacial and insulating layers. A second source/drain is formed above the first source/drain. The method comprises forming at least one semiconductor fin. An interfacial layer is formed in contact with sidewalls of the semiconductor fin. An insulating layer is formed in contact with the interfacial layer. The interfacial layer and the insulating layer are encapsulated by one or more conductive gate layers.