公开(公告)号：US20170194510A1

公开(公告)日：2017-07-06

申请号：US15467555

申请日：2017-03-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L29/786 ,  H01L21/306 ,  H01L29/775 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L21/0228 ,  H01L21/02603 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.

公开(公告)号：US09691715B2

公开(公告)日：2017-06-27

申请号：US15093350

申请日：2016-04-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Isaac Lauer ,  Tenko Yamashita ,  Jeffrey W. Sleight

IPC: H01L21/02 ,  H01L23/00 ,  H01L29/775 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L23/562 ,  B82Y10/00 ,  H01L21/02403 ,  H01L21/02603 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42356 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78696

Abstract: A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component. An anchor pad is formed along a span of the nanowire and configured to support the nanowire along the span to prevent sagging.

公开(公告)号：US20170117373A1

公开(公告)日：2017-04-27

申请号：US15400178

申请日：2017-01-06

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Robert H. Dennard ,  Isaac Lauer ,  Ramachandran Muralidhar

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/42356 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/41758 ,  H01L29/4908 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/66772 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method of forming a MOSFET device is provided including: providing an SOI wafer; forming a dummy gate oxide and dummy gates on portions of the SOI layer that serve as channel regions of the device; forming spacers and doped source/drain regions in the SOI layer on opposite sides of the dummy gates; depositing a gap fill dielectric; removing the dummy gates/gate oxide; recessing areas of the SOI layer exposed by removal of the dummy gates forming one or more u-shaped grooves that extend part-way through the SOI layer such that a thickness of the SOI layer remaining in the channel regions is less than a thickness of the SOI layer in the doped source/drain regions under the spacers; and forming u-shaped replacement gate stacks in the u-shaped grooves such that u-shaped channels are formed in fully depleted regions of the SOI layer adjacent to the u-shaped replacement gate stacks.

公开(公告)号：US09627330B2

公开(公告)日：2017-04-18

申请号：US14798007

申请日：2015-07-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Isaac Lauer ,  Tenko Yamashita ,  Jeffrey W. Sleight

IPC: H01L29/423 ,  H01L29/06 ,  H01L23/00 ,  H01L29/775 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L23/562 ,  B82Y10/00 ,  H01L21/02403 ,  H01L21/02603 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42356 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78696

Abstract: A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component. An anchor pad is formed along a span of the nanowire and configured to support the nanowire along the span to prevent sagging.

公开(公告)号：US20170069763A1

公开(公告)日：2017-03-09

申请号：US14846428

申请日：2015-09-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/775 ,  H01L29/06

CPC classification number: H01L21/0228 ,  H01L21/02603 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.

公开(公告)号：US20170069734A1

公开(公告)日：2017-03-09

申请号：US15254442

申请日：2016-09-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L29/66 ,  H01L21/306 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L21/0228 ,  H01L21/02603 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.

公开(公告)号：US09564502B2

公开(公告)日：2017-02-07

申请号：US15243065

申请日：2016-08-22

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L29/06 ,  H01L29/423 ,  H01L27/12 ,  H01L27/092 ,  H01L21/84 ,  H01L29/49

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L21/82345 ,  H01L21/84 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0673 ,  H01L29/1079 ,  H01L29/401 ,  H01L29/495 ,  H01L29/66439 ,  H01L29/775

Abstract: In one aspect, a method of forming a CMOS device with multiple transistors having different Vt's is provided which includes: forming nanowires and pads on a wafer, wherein the nanowires are suspended at varying heights above an oxide layer of the wafer; and forming gate stacks of the transistors at least partially surrounding portions of each of the nanowires by: i) depositing a conformal gate dielectric around the nanowires and on the wafer beneath the nanowires; ii) depositing a conformal workfunction metal on the conformal gate dielectric around the nanowires and on the wafer beneath the nanowires, wherein an amount of the conformal workfunction metal deposited around the nanowires is varied based on the varying heights at which the nanowires are suspended over the oxide layer; and iii) depositing a conformal poly-silicon layer on the conformal workfunction metal around the nanowires and on the wafer beneath the nanowires.

Abstract translation: 一方面，提供一种形成具有不同Vt的多个晶体管的CMOS器件的方法，其包括：在晶片上形成纳米线和焊盘，其中所述纳米线在所述晶片的氧化物层上方的不同高度处悬挂; 以及通过以下步骤，至少部分地围绕所述纳米线中的每一个的所述晶体管的栅堆叠：i）在所述纳米线下方的所述纳米线周围和所述晶片上沉积共形栅极电介质; ii）在纳米线周围的纳米线周围和纳米线下方的晶片上的共形栅极电介质上沉积保形功函数金属，其中沉积在纳米线周围的一定量的共形功函数金属基于纳米线悬挂在该纳米线上的变化高度而变化 氧化层; 以及iii）在纳米线周围的纳米线周围的纳米线下方的晶片上在保形功函数金属上沉积共形多晶硅层。

公开(公告)号：US20170005090A1

公开(公告)日：2017-01-05

申请号：US14788297

申请日：2015-06-30

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Robert H. Dennard ,  Isaac Lauer ,  Ramachandran Muralidhar ,  Ghavam G. Shahidi

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/10 ,  H01L21/28 ,  H01L29/49 ,  H01L21/308 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L27/0886 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/3081 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818

Abstract: In one aspect, a method of forming finFET devices is provided which includes patterning fins in a wafer; forming dummy gates over the fins; forming spacers on opposite sides of the dummy gates; depositing a gap fill oxide on the wafer, filling any gaps between the spacers; removing the dummy gates forming gate trenches; trimming the fins within the gate trenches such that a width of the fins within the gate trenches is less than the width of the fins under the spacers adjacent to the gate trenches, wherein u-shaped grooves are formed in sides of the fins within the gate trenches; and forming replacement gate stacks in the gate trenches, wherein portions of the fins adjacent to the replacement gate stacks serve as source and drain regions of the finFET devices.

Abstract translation: 在一个方面，提供了一种形成finFET器件的方法，其包括在晶片中构图鳍片; 在翅片上形成虚拟门; 在伪栅极的相对侧上形成间隔物; 在晶片上沉积间隙填充氧化物，填充间隔物之间​​的任何间隙; 去除形成栅极沟槽的虚拟栅极; 在栅极沟槽内修整散热片，使得栅极沟槽内的散热片的宽度小于在与栅极沟槽相邻的隔板下面的散热片的宽度，其中U形沟槽形成在栅极内的鳍片的侧面 沟渠 以及在所述栅极沟槽中形成替换栅极堆叠，其中与所述替代栅极堆叠相邻的所述鳍片的部分用作所述finFET器件的源极和漏极区域。

公开(公告)号：US09536794B2

公开(公告)日：2017-01-03

申请号：US14671041

申请日：2015-03-27

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L27/1203 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66772 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78654 ,  H01L29/78696 ,  H01L2029/42388

Abstract: In one aspect, a method of forming a CMOS device includes forming nanowires suspended over a BOX, wherein a first/second one or more of the nanowires are suspended at a first/second suspension height over the BOX, and wherein the first suspension height is greater than the second suspension height; depositing a conformal gate dielectric on the BOX and around the nanowires wherein the conformal gate dielectric deposited on the BOX is i) in a non-contact position with the conformal gate dielectric deposited around the first one or more of the nanowires, and ii) is in direct physical contact with the conformal gate dielectric deposited around the second one or more of the nanowires such that the BOX serves as an oxygen source during growth of a conformal oxide layer at the interface between the conformal gate dielectric and the second one or more of the nanowires.

Abstract translation: 在一个方面，形成CMOS器件的方法包括形成悬挂在BOX上的纳米线，其中第一/第二个或多个纳米线在BOX上的第一/第二悬架高度处悬挂，并且其中第一悬浮高度为 大于第二悬架高度; 在BOX上并围绕纳米线沉积共形栅极电介质，其中沉积在BOX上的共形栅极电介质是i）与保形栅极电介质沉积在第一个或多个纳米线周围的非接触位置，以及ii）是 与围绕第二个或多个纳米线沉积的共形栅极电介质直接物理接触，使得BOX在保形氧化物层在共形栅极电介质和第二个或多个之间的界面处生长期间用作氧源 纳米线。

公开(公告)号：US20160359011A1

公开(公告)日：2016-12-08

申请号：US15243065

申请日：2016-08-22

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/06 ,  H01L21/84 ,  H01L27/12 ,  H01L27/092

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L21/82345 ,  H01L21/84 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0673 ,  H01L29/1079 ,  H01L29/401 ,  H01L29/495 ,  H01L29/66439 ,  H01L29/775

Abstract: In one aspect, a method of forming a CMOS device with multiple transistors having different Vt's is provided which includes: forming nanowires and pads on a wafer, wherein the nanowires are suspended at varying heights above an oxide layer of the wafer; and forming gate stacks of the transistors at least partially surrounding portions of each of the nanowires by: i) depositing a conformal gate dielectric around the nanowires and on the wafer beneath the nanowires; ii) depositing a conformal workfunction metal on the conformal gate dielectric around the nanowires and on the wafer beneath the nanowires, wherein an amount of the conformal workfunction metal deposited around the nanowires is varied based on the varying heights at which the nanowires are suspended over the oxide layer; and iii) depositing a conformal poly-silicon layer on the conformal workfunction metal around the nanowires and on the wafer beneath the nanowires.

Abstract translation: 一方面，提供一种形成具有不同Vt的多个晶体管的CMOS器件的方法，其包括：在晶片上形成纳米线和焊盘，其中所述纳米线在所述晶片的氧化物层上方的不同高度处悬挂; 以及通过以下步骤，至少部分地围绕所述纳米线中的每一个的所述晶体管的栅堆叠：i）在所述纳米线下方的所述纳米线周围和所述晶片上沉积共形栅极电介质; ii）在纳米线周围的纳米线周围和纳米线下方的晶片上的共形栅极电介质上沉积保形功函数金属，其中沉积在纳米线周围的一定量的共形功函数金属基于纳米线悬挂在该纳米线上的变化高度而变化 氧化层; 以及iii）在纳米线周围的纳米线周围的纳米线下方的晶片上在保形功函数金属上沉积共形多晶硅层。