公开(公告)号：US20060034117A1

公开(公告)日：2006-02-16

申请号：US11201495

申请日：2005-08-11

申请人： Won-Cheol Jeong ,  Ki-Nam Kim ,  Hong-Sik Jeong ,  Gi-Tae Jeong ,  Jae-Hyun Park

发明人： Won-Cheol Jeong ,  Ki-Nam Kim ,  Hong-Sik Jeong ,  Gi-Tae Jeong ,  Jae-Hyun Park

IPC分类号： G11C11/14

CPC分类号： G11C11/16

摘要： Methods are provided for operating a magnetic random access memory device including a memory cell having a magnetic tunnel junction structure on a substrate. In particular, a writing current pulse may be provided through the magnetic tunnel junction structure, and a writing magnetic field pulse may be provided through the magnetic tunnel junction structure. In addition, at least a portion of the writing magnetic field pulse may be overlapping in time with respect to at least a portion of the writing current pulse, and at least a portion of the writing current pulse and/or at least a portion of the writing magnetic field pulse may be non-overlapping in time with respect to the other. Related devices are also discussed.

摘要翻译： 提供了用于操作包括在衬底上具有磁性隧道结结构的存储单元的磁性随机存取存储器件的方法。 特别地，可以通过磁性隧道结结构提供写入电流脉冲，并且可以通过磁性隧道结结构提供写入磁场脉冲。 此外，写入磁场脉冲的至少一部分可以相对于写入电流脉冲的至少一部分在时间上重叠，并且写入电流脉冲的至少一部分和/或至少一部分 写入磁场脉冲可能在时间上相对于另一个不重叠。 还讨论了相关设备。

公开(公告)号：US06828617B2

公开(公告)日：2004-12-07

申请号：US10142773

申请日：2002-05-13

申请人： Hyung-Soo Uh ,  Sang-Ho Song ,  Ki-Nam Kim

发明人： Hyung-Soo Uh ,  Sang-Ho Song ,  Ki-Nam Kim

IPC分类号： H01L2976

CPC分类号： H01L27/10855 ,  H01L27/10894 ,  H01L28/60 ,  H01L28/90

摘要： A method for fabricating a capacitor of a semiconductor device, and a capacitor made in accordance with the method, wherein the method includes forming a plate electrode polysilicon layer on a semiconductor substrate having a cell array region and a core/peripheral circuit region. The plate electrode polysilicon layer in the cell array region is patterned to form an opening, wherein the inner wall of the opening is used as a plate electrode. After forming a dielectric layer in the opening, a storage node is formed as a spacer on the dielectric layer on the inner wall of the opening. The plate electrode polysilicon layer in the core/peripheral circuit region remains to provide the same height between the cell array region where the cell capacitor is formed and the core/peripheral circuit region.

摘要翻译： 一种制造半导体器件的电容器的方法和根据该方法制造的电容器，其中该方法包括在具有单元阵列区域和核心/外围电路区域的半导体衬底上形成平板电极多晶硅层。 将单元阵列区域中的平板电极多晶硅层图案化以形成开口，其中开口的内壁用作平板电极。 在开口中形成电介质层之后，在开口的内壁上的电介质层上形成作为间隔物的存储节点。 芯/外围电路区域中的平板电极多晶硅层保持为在形成单元电容器的单元阵列区域和核心/外围电路区域之间提供相同的高度。

公开(公告)号：US06753227B2

公开(公告)日：2004-06-22

申请号：US10437881

申请日：2003-05-13

申请人： Chang-Hyun Cho ,  Gwan-Hyeob Koh ,  Ki-Nam Kim

发明人： Chang-Hyun Cho ,  Gwan-Hyeob Koh ,  Ki-Nam Kim

IPC分类号： H01L21336

CPC分类号： H01L21/823807 ,  H01L21/28061 ,  H01L21/823892 ,  H01L29/4933

摘要： A method of fabricating a MOS transistor is provided. According to the method, a rapid thermal anneal is applied to a semiconductor substrate having active regions doped with well impurity ions and channel impurity ions. Thus, during implantation of the well and the channel impurity ions, crystalline defects resulting from the implantation can be cured by the rapid thermal anneal.

摘要翻译： 提供一种制造MOS晶体管的方法。 根据该方法，将快速热退火应用于具有掺杂有良好杂质离子和沟道杂质离子的有源区的半导体衬底。 因此，在注入阱和通道杂质离子期间，通过快速热退火可以固化由植入产生的结晶缺陷。

公开(公告)号：US06562697B1

公开(公告)日：2003-05-13

申请号：US10093295

申请日：2002-03-07

申请人： Chang-Hyun Cho ,  Ki-Nam Kim ,  Sang-Hyeon Lee

发明人： Chang-Hyun Cho ,  Ki-Nam Kim ,  Sang-Hyeon Lee

IPC分类号： H01L2176

CPC分类号： H01L21/76237 ,  H01L21/823481

摘要： Active areas of integrated circuits can be formed by implanting first ions into a first active area of a substrate adjacent to an isolation structure in the substrate and between a source and a drain region of the integrated circuit to provide a first concentration of ions in the first active area. Second ions are implanted into the first active area and a second active area of the substrate adjacent to the first active area and spaced-apart from the isolation structure on the substrate to provide a second concentration of ions in the second active area and a third concentration of ions in the first active area that is greater than the first and second concentrations. As a result, the level of ion concentration can be higher at the edge of an active channel region than at the center of the channel. The increased concentration of ions in the active area adjacent to the side wall of the trench may reduce a current between the source and drain regions of the transistor when voltage that is less than a threshold voltage of the transistor is applied to the gate electrode of the transistor. Thus, a reduction in the threshold voltage of the transistor can be inhibited. Integrated circuit transistors are also disclosed.

摘要翻译： 可以通过将第一离子注入与衬底中的隔离结构相邻的衬底的第一有源区域中并且在集成电路的源极和漏极区域之间注入第一离子以形成第一离子的第一浓度来形成集成电路的有源区域 活动区域。 将第二离子注入与第一有源区相邻的第一有源区和衬底的第二有源区，并与衬底上的隔离结构间隔开，以在第二有源区中提供第二离子浓度，并且将第三浓度 的第一活性区域中的离子，其大于第一和第二浓度。 结果，在有源沟道区的边缘处，离子浓度的水平可高于通道中心处的离子浓度。 当沟槽的侧壁附近的有源区域中的离子浓度的增加可以减小晶体管的源极和漏极区域之间的电流，当小于晶体管的阈值电压的电压被施加到晶体管的栅电极时 晶体管。 因此，可以抑制晶体管的阈值电压的降低。 还公开了集成电路晶体管。

公开(公告)号：US06518671B1

公开(公告)日：2003-02-11

申请号：US09699591

申请日：2000-10-30

申请人： Won-Suk Yang ,  Yoo-Sang Hwang ,  Hong-Sik Jeong ,  Ki-Nam Kim

发明人： Won-Suk Yang ,  Yoo-Sang Hwang ,  Hong-Sik Jeong ,  Ki-Nam Kim

IPC分类号： H02L2348

CPC分类号： H01L21/76897 ,  H01L21/76829 ,  H01L21/76834 ,  H01L27/10882 ,  H01L27/10894

摘要： An etch-stop layer is selectively provided between layers of a multiple-layered circuit in a selective manner so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer. In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense

摘要翻译： 选择性地在多层电路的层之间选择性地提供蚀刻停止层，以便允许随后的制造过程中的杂质脱气。 蚀刻停止层形成在下面的螺柱上，以便在形成在上层中的上覆螺柱的形成期间用作对准目标。 以这种方式，可以相对致密地制造多层电路，例如存储器件

公开(公告)号：US06242332B1

公开(公告)日：2001-06-05

申请号：US09384281

申请日：1999-08-27

申请人： Chang-Hyun Cho ,  Tae-Young Chung ,  Ki-Nam Kim

发明人： Chang-Hyun Cho ,  Tae-Young Chung ,  Ki-Nam Kim

IPC分类号： H01L213205

CPC分类号： H01L21/76897

摘要： The size of a pad in the present invention is reduced, thereby preventing a polymer etch-stop, suppressing a short between a gate and a gate conductive layer exposed by the damage of an oxide layer covering the gate conductive layer, and extending a top surface area of a pad beyond the technical limitation of a photo equipment. As a result, it is possible to greatly secure the alignment of a buried contact electrically connected to the pad.

摘要翻译： 本发明的焊盘的尺寸减小，从而防止聚合物蚀刻停止，从而抑制由覆盖栅极导电层的氧化物层的损坏而露出的栅极和栅极导电层之间的短路，并且延伸顶表面 超过照相设备的技术限制的垫的面积。 结果，可以极大地确保电连接到焊盘的埋入触点的对准。

公开(公告)号：US06198651B1

公开(公告)日：2001-03-06

申请号：US09149366

申请日：1998-09-08

申请人： Jin-Woo Lee ,  Dong-Jin Jung ,  Ki-Nam Kim

发明人： Jin-Woo Lee ,  Dong-Jin Jung ,  Ki-Nam Kim

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： Ferroelectric memory devices include a plate line, a bit line, a ferroelectric memory cell containing a first access transistor and a first ferroelectric capacitor electrically connected in series between the bit line and the plate line, and a word line electrically connected to a gate electrode of the first access transistor. A row decoder and a preferred plate line pulse generator are also provided to generate a write voltage of first magnitude (e.g., Vcc) on the plate line during a write time interval and a read voltage of a second magnitude (e.g., Vcc+&agr;), greater than the first magnitude, on the plate line during a read time interval. These different magnitudes of the write and read voltage for the plate line are generated in response to a control signal (CP), so that during a read operation, the magnitude of the change in voltage across the ferroelectric capacitor will be sufficient to enable a complete charge transfer of 2QR when the ferroelectric memory cell is storing a data 1 value. The plate line pulse generator may comprise a pulse generator, a voltage boosting circuit having an input electrically coupled to an output of the pulse generator and a switch circuit to electrically couple an output of the pulse generator to an output of the plate line pulse generator when the control signal is in a first logic state (during a write operation) and electrically couple an output of the voltage boosting circuit to the output of the plate line pulse generator when the control signal is in a second logic state (during a read operation).

摘要翻译： 铁电存储器件包括板线，位线，含有第一存取晶体管的铁电存储单元和串联地电连接在位线和板线之间的第一铁电电容器，以及电连接到位线 第一个存取晶体管。 还提供行解码器和优选的板线脉冲发生器，以在写入时间间隔期间在板线上产生第一幅度（例如，Vcc）的写入电压和第二幅度的读取电压（例如，Vcc +α） ，大于第一幅度，在读取时间间隔内的板条线上。 响应于控制信号（CP）产生板线的写入和读取电压的这些不同的大小，使得在读取操作期间，铁电电容器两端的电压变化的幅度将足以使得能够完成 当铁电存储单元正在存储数据1值时，2QR的电荷转移。 板线脉冲发生器可以包括脉冲发生器，具有电耦合到脉冲发生器的输出的输入的升压电路和用于将脉冲发生器的输出电耦合到板线脉冲发生器的输出的开关电路， 控制信号处于第一逻辑状态（在写入操作期间），并且当控制信号处于第二逻辑状态（在读取操作期间）时将升压电路的输出电耦合到板线脉冲发生器的输出， 。

公开(公告)号：US6136657A

公开(公告)日：2000-10-24

申请号：US315341

申请日：1999-05-20

申请人： Won-Suk Yang ,  Chang-Hyun Cho ,  Ki-Nam Kim

发明人： Won-Suk Yang ,  Chang-Hyun Cho ,  Ki-Nam Kim

IPC分类号： H01L27/108 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L29/423 ,  H01L21/336 ,  H01L21/31

CPC分类号： H01L29/42368 ,  H01L21/28167 ,  H01L21/823462 ,  H01L21/28211 ,  H01L27/10873 ,  H01L27/10894 ,  Y10S438/981

摘要： A method for fabricating a semiconductor device with different gate oxide layers is provided. In this method, oxidation is controlled in accordance with the active area dimension so that the oxide grows more thinly at a wider active width in a peripheral region, and grows more thickly at a narrower active width in a cell array region. In this method, a gate pattern is formed over a semiconductor substrate having different active areas. Gate spacer are formed and an active-dimension-dependant oxidation process is then performed to grow oxide layers of different thicknesses in the cell array region and the peripheral region.

摘要翻译： 提供一种制造具有不同栅氧化层的半导体器件的方法。 在该方法中，根据有源面积尺寸控制氧化，使得氧化物在周边区域中以更宽的有源宽度更薄地生长，并且在单元阵列区域中以较窄的有源宽度生长更厚。 在该方法中，在具有不同有源区域的半导体衬底上形成栅极图案。 形成栅极间隔物，然后执行活性尺寸依赖性氧化工艺以在电池阵列区域和外围区域中生长不同厚度的氧化物层。