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    SEMICONDUCTOR STORAGE DEVICE
    123.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE 有权
    半导体存储设备

    公开(公告)号：US20110024828A1

    公开(公告)日：2011-02-03

    申请号：US12922313

    申请日：2009-04-14

    Applicant: Kiyoshi Takeuchi

    Inventor： Kiyoshi Takeuchi

    IPC: H01L27/11

    CPC classification number: H01L27/1104 ,  H01L21/823821 ,  H01L21/823885 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11

    Abstract: An SRAM cell using a vertical MISFET is provided, wherein underside source/drain areas of a first access transistor, a first driving transistor and a first load transistor are connected together, and further connected to gates of a second driving transistor and a second load transistor. Underside source/drain areas of a second access transistor, the second driving transistor and the second load transistor are connected together, and further connected to gates of the first driving transistor and the first load transistor. A first arrangement of the first access transistor, the first driving transistor and the first load transistor, and a second arrangement of the second access transistor, the second driving transistor and the second load transistor are symmetric to each other.

    Abstract translation: 提供了使用垂直MISFET的SRAM单元，其中第一存取晶体管，第一驱动晶体管和第一负载晶体管的下侧源极/漏极区域连接在一起，并且还连接到第二驱动晶体管和第二负载晶体管的栅极 。 第二存取晶体管的下侧源极/漏极区域，第二驱动晶体管和第二负载晶体管连接在一起，并且还连接到第一驱动晶体管和第一负载晶体管的栅极。 第一存取晶体管，第一驱动晶体管和第一负载晶体管的第一布置以及第二存取晶体管的第二布置，第二驱动晶体管和第二负载晶体管彼此对称。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    124.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20110018056A1

    公开(公告)日：2011-01-27

    申请号：US12922316

    申请日：2009-03-27

    Applicant: Kiyoshi Takeuchi

    Inventor： Kiyoshi Takeuchi

    IPC: H01L27/088 ,  H01L21/8234

    CPC classification number: H01L23/535 ,  H01L21/76895 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/7827 ,  H01L29/78642 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A first local wiring includes a convex portion protruding from a base and a protrusion protruding from a side surface of the convex portion. The convex portion of the first local wiring is connected to a lower conductive region of a first transistor while the protrusion is connected to a gate electrode of a second transistor. Moreover, the lower surface of the protrusion of the first local wiring is arranged at a height equal to or lower than the upper surface of the gate electrode of the second transistor.

    Abstract translation: 第一局部布线包括从基部突出的凸部和从凸部的侧面突出的突起。 第一局部布线的凸部连接到第一晶体管的下导电区域，同时突起连接到第二晶体管的栅电极。 此外，第一局部布线的突起的下表面布置在等于或低于第二晶体管的栅电极的上表面的高度。

    VARIATION SIMULATION SYSTEM, METHOD FOR DETERMINING VARIATIONS, APPARATUS FOR DETERMINING VARIATIONS AND PROGRAM
    125.
    发明申请
    VARIATION SIMULATION SYSTEM, METHOD FOR DETERMINING VARIATIONS, APPARATUS FOR DETERMINING VARIATIONS AND PROGRAM 审中-公开
    变化模拟系统，确定变化的方法，用于确定变化和程序的装置

    公开(公告)号：US20100217568A1

    公开(公告)日：2010-08-26

    申请号：US12278884

    申请日：2006-11-16

    Applicant: Kiyoshi Takeuchi

    Inventor： Kiyoshi Takeuchi

    IPC: G06F17/11 ,  G06F17/16 ,  G06F17/50

    CPC classification number: G06F17/5009 ,  G06F2217/10 ,  G06F2217/78

    Abstract: Disclosed is a variation simulation system including a variation analysis unit that acquires the results of statistical analysis of variations of characteristics of a plural number of target devices, a model analysis unit that acquires the results of analysis showing how the characteristics respond to variations of a parameter with respect to a model for simulation that simulates each target device, a fitting execution unit that collates the results obtained by the variation analysis unit to those obtained by the model analysis unit and determines the manner of variations of the parameter in order to reproduce the variations of each target device in accordance with the model, and a result output unit that outputs the information on the manner of variations of the parameter determined by the fitting execution unit. A transformation matrix is determined by multiplying a pseudo inverse matrix of a response matrix, a matrix made up of principal component vectors and an arbitrary unitary matrix.

    Abstract translation: 公开了一种变型模拟系统，其包括：变量分析单元，其获取多个目标设备的特性变化的统计分析结果;模型分析单元，其获取分析结果，显示特征如何响应于参数的变化 相对于模拟每个目标装置的模拟模型，拟合执行单元将由变化分析单元获得的结果与由模型分析单元获得的结果进行比较，并且确定参数的变化方式以便再现变化 以及结果输出单元，其输出关于由拟合执行单元确定的参数的变化方式的信息。 通过将响应矩阵的伪逆矩阵，由主成分矢量构成的矩阵和任意的酉矩阵相乘来确定变换矩阵。

    Semiconductor device having vertical field effect transistor and method of manufacturing the same
    126.
    发明申请
    Semiconductor device having vertical field effect transistor and method of manufacturing the same 审中-公开
    具有垂直场效应晶体管的半导体器件及其制造方法

    公开(公告)号：US20100052055A1

    公开(公告)日：2010-03-04

    申请号：US12461433

    申请日：2009-08-11

    Applicant: Kiyoshi Takeuchi

    Inventor： Kiyoshi Takeuchi

    IPC: H01L27/092

    CPC classification number: H01L29/78642 ,  H01L21/823487 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/42392

    Abstract: A semiconductor device has: an insulating substrate; a first semiconductor layer of a first conductivity type formed on the insulating substrate; a first vertical field effect transistor of the first conductivity type, one of whose source and drain being formed on the first semiconductor layer; a second semiconductor layer of a second conductivity type formed on the insulating substrate; and a second vertical field effect transistor of the second conductivity type, one of whose source and drain being formed on the second semiconductor layer. The first semiconductor layer and the second semiconductor layer are directly in contact with each other.

    Abstract translation: 半导体器件具有：绝缘基板; 形成在绝缘基板上的第一导电类型的第一半导体层; 第一导电类型的第一垂直场效应晶体管，其源极和漏极之一形成在第一半导体层上; 形成在所述绝缘基板上的第二导电类型的第二半导体层; 以及第二导电类型的第二垂直场效应晶体管，其源极和漏极之一形成在第二半导体层上。 第一半导体层和第二半导体层彼此直接接触。

    Sheet Plasma Film-Forming Apparatus
    127.
    发明申请
    Sheet Plasma Film-Forming Apparatus 审中-公开
    薄片等离子体成膜装置

    公开(公告)号：US20090314206A1

    公开(公告)日：2009-12-24

    申请号：US12096538

    申请日：2006-11-29

    Applicant: Masao Marunaka ,  Takayuki Tsuchiya ,  Atsuhiro Terakura ,  Kiyoshi Takeuchi

    Inventor： Masao Marunaka ,  Takayuki Tsuchiya ,  Atsuhiro Terakura ,  Kiyoshi Takeuchi

    IPC: C23C16/513

    CPC classification number: H01J37/3266 ,  C23C14/046 ,  C23C14/35 ,  H01J37/32009 ,  H01L21/2855 ,  H01L21/76877

    Abstract: A sheet plasma film forming apparatus (100) of the present invention includes: a plasma gun (40) which can emit source plasma (22) in a transport direction; a sheet plasma converting chamber (20) including a transport space (21) extending in the transport direction; a pair of first magnetic field generating means (24A, 24B) disposed so as to sandwich the transport space (21) such that same poles thereof face each other; a film forming chamber (30) including a film forming space (31) which communicates with the transport space (21); and a pair of second magnetic field generating means (32, 33) disposed so as to sandwich the film forming space such that different poles thereof face each other, wherein: while moving in the transport space (21), the source plasma (22) is converted by a magnetic field of the pair of first magnetic field generating means (24A, 24B) into sheet-shaped plasma spreading along a main surface S including a center; and while moving in the film forming space (31), the sheet-shaped plasma 27 is caused to convexly project from the main surface S by a magnetic field of the pair of second magnetic field generating means (32, 33).

    Abstract translation: 本发明的片状等离子体成膜装置（100）包括：能够沿输送方向发射源极等离子体（22）的等离子体枪（40） 包括沿输送方向延伸的输送空间（21）的片状等离子体转换室（20） 一对第一磁场产生装置（24A，24B），其设置成夹着输送空间（21）使得相同的磁极彼此面对; 成膜室（30），其包括与所述运送空间（21）连通的成膜空间（31）; 以及一对第二磁场产生装置（32,33），其设置成夹住成膜空间，使得其不同的极彼此面对，其中：在运送空间（21）中移动时，源等离子体（22） 被一对第一磁场产生装置（24A，24B）的磁场转换成包括中心的主表面S的片状等离子体扩散; 并且在成膜空间（31）中移动的同时，通过该对第二磁场产生装置（32,33）的磁场使片状等离子体27从主表面S凸出。

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