中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

352 records (took 0.023 seconds)

    Methods of operating a memory device having a buried boosting plate
    122.
    发明授权
    Methods of operating a memory device having a buried boosting plate 有权
    操作具有埋地升压板的存储器件的方法

    公开(公告)号：US09281073B2

    公开(公告)日：2016-03-08

    申请号：US14159198

    申请日：2014-01-20

    Applicant: Micron Technology, Inc.

    Inventor： Akira Goda

    IPC: G11C16/10 ,  G11C16/34 ,  G11C7/22

    CPC classification number: G11C16/3427 ,  G11C5/146 ,  G11C7/222 ,  G11C16/10 ,  H01L27/11546

    Abstract: Memory devices are disclosed, such as those that include a semiconductor-on-insulator (SOI) NAND memory array having a boosting plate. The boosting plate may be disposed in an insulator layer of the SOI substrate such that the boosting plate exerts a capacitive coupling effect on a p-well of the memory array. Such a boosting plate may be used to boost the p-well during program and erase operations of the memory array. During a read operation, the boosting plate may be grounded to minimize interaction with p-well. Systems including the memory array and methods of operating the memory array are also disclosed.

    Abstract translation: 公开了存储器件，例如包括具有升压板的绝缘体上半导体（SOI）NAND存储器阵列的存储器件。 升压板可以设置在SOI衬底的绝缘体层中，使得升压板对存储器阵列的p阱施加电容耦合效应。 这种升压板可用于在存储器阵列的编程和擦除操作期间升压p阱。 在读取操作期间，升压板可以接地以最小化与p阱的相互作用。 还公开了包括存储器阵列的系统和操作存储器阵列的方法。

    Methods for forming a string of memory cells and apparatuses having a vertical string of memory cells including metal
    124.
    发明授权
    Methods for forming a string of memory cells and apparatuses having a vertical string of memory cells including metal 有权
    用于形成具有包括金属的存储单元的垂直串的存储器单元串和设备的方法

    公开(公告)号：US09041090B2

    公开(公告)日：2015-05-26

    申请号：US13894631

    申请日：2013-05-15

    Applicant: Micron Technology, Inc.

    Inventor： Fatma Arzum Simsek-Ege ,  Akira Goda ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01L27/115 ,  H01L27/105 ,  H01L29/792 ,  H01L29/788 ,  H01L29/76 ,  H01L21/8239 ,  H01L21/336 ,  H01L21/04 ,  H01L29/66

    CPC classification number: H01L27/11556 ,  H01L27/1052 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/792

    Abstract: Methods for forming a string of memory cells and apparatuses having a vertical string of memory cells are disclosed. One such string of memory cells can be formed at least partially in a stack of materials comprising a plurality of alternating levels of control gate material and insulator material. A memory cell of the string can include floating gate material adjacent to a level of control gate material of the levels of control gate material. The memory cell can also include tunnel dielectric material adjacent to the floating gate material. The level of control gate material and the tunnel dielectric material are adjacent opposing surfaces of the floating gate material. The memory cell can include metal along an interface between the tunnel dielectric material and the floating gate material. The memory cell can further include a semiconductor material adjacent to the tunnel dielectric material.

    Abstract translation: 公开了形成一串存储单元的方法和具有垂直的存储单元串的装置。 一个这样的存储单元串可以至少部分地形成为包括多个交替级控制栅极材料和绝缘体材料的堆叠材料。 串的存储单元可以包括与控制栅极材料的电平的控制栅极材料的级别相邻的浮动栅极材料。 存储单元还可以包括与浮栅材料相邻的隧道介电材料。 控制栅极材料和隧道电介质材料的水平面与浮栅材料的相邻表面相邻。 存储单元可以沿着隧道介电材料和浮栅材料之间的界面包括金属。 存储单元还可以包括与隧道电介质材料相邻的半导体材料。

    Memory arrays where a distance between adjacent memory cells at one end of a substantially vertical portion is greater than a distance between adjacent memory cells at an opposing end of the substantially vertical portion and formation thereof
    125.
    发明授权
    Memory arrays where a distance between adjacent memory cells at one end of a substantially vertical portion is greater than a distance between adjacent memory cells at an opposing end of the substantially vertical portion and formation thereof 有权
    存储器阵列，其中在基本垂直部分的一端处的相邻存储器单元之间的距离大于在基本垂直部分的相对端处的相邻存储器单元之间的距离及其形成

    公开(公告)号：US08951865B2

    公开(公告)日：2015-02-10

    申请号：US13746578

    申请日：2013-01-22

    Applicant: Micron Technology, Inc.

    Inventor： Akira Goda

    IPC: H01L21/336 ,  H01L29/66 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L29/66666 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

    Abstract: Memory arrays and their formation are disclosed. One such memory array has a string of series-coupled memory cells with a substantially vertical portion. A distance between adjacent memory cells at one end of the substantially vertical portion is greater than a distance between adjacent memory cells at an opposing end of the substantially vertical portion. For other embodiments, thicknesses of respective control gates of the memory cells and/or thicknesses of the dielectrics between successively adjacent control gates may increase as the distances of the respective control gates/dielectrics from the opposing end of the substantially vertical portion increase.

    Abstract translation: 公开了存储器阵列及其形成。 一个这样的存储器阵列具有串联耦合的存储器单元串，其具有基本垂直的部分。 在基本垂直部分的一端处的相邻存储单元之间的距离大于在基本垂直部分的相对端处的相邻存储单元之间的距离。 对于其他实施例，存储单元的相应控制栅极的厚度和/或连续相邻的控制栅极之间的电介质的厚度可以随着各个控制栅极/电介质与基本垂直部分的相对端的距离增加而增加。

    METHODS FOR FORMING A STRING OF MEMORY CELLS AND APPARATUSES HAVING A VERTICAL STRING OF MEMORY CELLS INCLUDING METAL
    126.
    发明申请
    METHODS FOR FORMING A STRING OF MEMORY CELLS AND APPARATUSES HAVING A VERTICAL STRING OF MEMORY CELLS INCLUDING METAL 有权
    形成一个记忆细胞的方法和具有包括金属在内的垂直存储器细胞的装置

    公开(公告)号：US20140339621A1

    公开(公告)日：2014-11-20

    申请号：US13894631

    申请日：2013-05-15

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Fatma Arzum Simsek-Ege ,  Akira Goda ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01L27/115

    CPC classification number: H01L27/11556 ,  H01L27/1052 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/792

    Abstract: Methods for forming a string of memory cells and apparatuses having a vertical string of memory cells are disclosed. One such string of memory cells can be formed at least partially in a stack of materials comprising a plurality of alternating levels of control gate material and insulator material. A memory cell of the string can include floating gate material adjacent to a level of control gate material of the levels of control gate material. The memory cell can also include tunnel dielectric material adjacent to the floating gate material. The level of control gate material and the tunnel dielectric material are adjacent opposing surfaces of the floating gate material. The memory cell can include metal along an interface between the tunnel dielectric material and the floating gate material. The memory cell can further include a semiconductor material adjacent to the tunnel dielectric material.

    Abstract translation: 公开了形成一串存储单元的方法和具有垂直的存储单元串的装置。 一个这样的存储单元串可以至少部分地形成为包括多个交替级控制栅极材料和绝缘体材料的堆叠材料。 串的存储单元可以包括与控制栅极材料的电平的控制栅极材料的级别相邻的浮动栅极材料。 存储单元还可以包括与浮栅材料相邻的隧道介电材料。 控制栅极材料和隧道电介质材料的水平面与浮栅材料的相邻表面相邻。 存储单元可以沿着隧道介电材料和浮栅材料之间的界面包括金属。 存储单元还可以包括与隧道电介质材料相邻的半导体材料。

    Sense operation in a memory device
    128.
    发明授权
    Sense operation in a memory device 有权
    存储设备中的感应操作

    公开(公告)号：US08780626B2

    公开(公告)日：2014-07-15

    申请号：US13762559

    申请日：2013-02-08

    Applicant: Micron Technology, Inc.

    Inventor： Yijie Zhao ,  Akira Goda ,  Mark A. Helm

    IPC: G11C16/04 ,  G11C16/26 ,  G11C16/34

    CPC classification number: G11C16/04 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3422 ,  G11C2211/5641

    Abstract: Methods for sensing and memory devices are disclosed. One such method for sensing determines a threshold voltage of an n-bit memory cell that is adjacent to an m-bit memory cell to be sensed. A control gate of the m-bit memory cell to be sensed is biased with a sense voltage adjusted responsive to the determined threshold voltage of the n-bit memory cell.

    Abstract translation: 公开了用于感测和存储器件的方法。 一种用于感测的方法确定与要感测的m位存储器单元相邻的n位存储器单元的阈值电压。 要感测的m位存储器单元的控制栅极利用响应于所确定的n位存储单元的阈值电压而调整的感测电压进行偏置。

Patent Agency Ranking