公开(公告)号：US11979147B2

公开(公告)日：2024-05-07

申请号：US17890568

申请日：2022-08-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi

IPC: H03K19/00 ,  H03K19/08 ,  H03K19/17736

CPC classification number: H03K19/0005 ,  H03K19/0813 ,  H03K19/17744

Abstract: Apparatuses, systems, and methods for memory initiated calibration. The memory includes a termination circuit with a tunable resistor and a calibration detection circuit with a replica tunable resistor. The calibration detection circuit measures a resistance of the replica tunable resistor and provides a calibration request signal if the resistance is outside a tolerance. Responsive to the calibration request signal, a controller of the memory schedules the memory for a calibration operation.

公开(公告)号：US20240070025A1

公开(公告)日：2024-02-29

申请号：US17822915

申请日：2022-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi

IPC: G06F11/10

CPC classification number: G06F11/1096

Abstract: Apparatuses, systems, and methods for module level error correction. Multiple memory devices a packaged together in a memory module. The module includes a module error correction code (ECC) circuit which pools information multiple memory devices on the module. In an example read operation, multiple memory devices each provide a codeword which includes data bits and parity bits. The codewords may include data bits provided along a data bus and parity bits provided along a parity bus. The ECC circuit pools the codewords and detects errors in the pooled codewords.

公开(公告)号：US11881247B2

公开(公告)日：2024-01-23

申请号：US18158316

申请日：2023-01-23

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G11C11/40 ,  G11C11/406 ,  G11C11/4063

CPC classification number: G11C11/40615 ,  G11C11/4063 ,  G11C11/40618 ,  G11C11/40622

Abstract: Apparatuses, systems, and methods for reset of row hammer detector circuits. A row hammer detector circuit includes a hash circuit configured to store a hash key and provide a first count value based on a hash between the hash key and a row address corresponding to a row of memory cells of a memory array. The row hammer detector circuit is configured to provide a match signal in response to the count value exceeding a threshold to cause a targeted refresh of a victim row adjacent the row of memory cells. In response to exit from a self-refresh mode, the hash circuit is configured to update the stored hash key with a new hash key.

公开(公告)号：US20230352064A1

公开(公告)日：2023-11-02

申请号：US17731024

申请日：2022-04-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi

IPC: G11C7/10

CPC classification number: G11C7/1039 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/1012 ,  G11C7/1048

Abstract: Apparatuses, systems, and methods for managing storage and retrieval of metadata at a memory. A metadata column address generator, during an metadata access operation, is configured to decode a subset of less than all of the bits of the column address to determine a metadata column address and a metadata column plane address corresponding to a particular one of column planes of a memory array. A column decoder is configured to facilitate a double cycle access operation to write data to or retrieve data from the plurality of column planes based on the column address and to write metadata to or retrieve metadata from a particular column corresponding to the metadata column address of the particular one of the column planes corresponding to the column plane address.

公开(公告)号：US20230350748A1

公开(公告)日：2023-11-02

申请号：US17730381

申请日：2022-04-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi

IPC: G06F11/10

CPC classification number: G06F11/106

Abstract: Apparatuses, systems, and methods for per row error correct and scrub (pRECS) information. There may be pRECS information associated with each row, and it may reflect a number of codewords stored along that row which were determined to include an error during error correct and scrub (ECS) operations. The memory may store the pRECS information in the memory array, for example, each row may store the pRECS information associated with that row.

公开(公告)号：US20230350581A1

公开(公告)日：2023-11-02

申请号：US17730992

申请日：2022-04-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/0655 ,  G06F3/0679

Abstract: Apparatuses, systems, and methods for managing access to metadata stored at a memory. To manage access to metadata, a mode register is configured to receive a metadata enable setting and to provide a metadata enable signal based on the metadata enable setting. A metadata access control circuit configured to receive a column address identifying a particular column to be accessed within a memory array. The metadata access control circuit blocks access to a column corresponding to the column address when the column address matches one of a plurality of particular column addresses designated for storage of metadata and the metadata enable signal has a first value, and permits access to a column corresponding to the column address when the column address is different than every one of the a plurality of particular column addresses designated for storage of metadata or the metadata enable signal has a second value.

公开(公告)号：US11803501B2

公开(公告)日：2023-10-31

申请号：US17505122

申请日：2021-10-19

Applicant: Micron Technology, Inc.

Inventor： Scott E. Smith ,  Randy Brian Drake ,  Brian Ladner ,  Thanh Kim Mai ,  Sujeet Ayyapureddi ,  Matthew Alan Prather

IPC: G06F13/40 ,  G06F11/10 ,  G06F13/16

CPC classification number: G06F13/4027 ,  G06F11/1076 ,  G06F13/1668

Abstract: The systems and methods described herein relate to a bi-directional data path (DQ) symbol map generated based on error correction operations. A device may include sub-wordline drivers and bi-directional data paths (DQs) that couple between the sub-wordline drivers and input/output (I/O) interface circuitry based on assignments indicated by the DQ symbol map. The assignments may be generated based on error correction operations performed on data of the memory bank. In particular, the DQ symbol map may be generated to avoid some conditions that, if occurring, may render one or more data errors uncorrectable. These systems and methods may reduce a likelihood of a data error associated with a DQ being uncorrectable.

公开(公告)号：US11646751B2

公开(公告)日：2023-05-09

申请号：US17348654

申请日：2021-06-15

Applicant: Micron Technology, Inc.

Inventor： Markus H. Geiger ,  Matthew A. Prather ,  Sujeet Ayyapureddi ,  C. Omar Benitez ,  Dennis Montierth

IPC: H03M13/09 ,  G06F11/10

CPC classification number: H03M13/095 ,  G06F11/1076

Abstract: Apparatuses, systems, and methods for multi-bit error detection. A memory device may store data bits and parity bits in a memory array. An error correction code (ECC) circuit may generate syndrome bits based on the data and parity bits and use the syndrome bits to correct up to a single bit error in the data and parity bits. A multi-bit error (MBE) detection circuit may detect an MBE in the data and parity based on at least one of the syndrome bits or the parity bits. For example, the MBE detection circuit may determine if the syndrome bits have a mapped or unmapped state and/or may compare the parity bits, data bits, and an additional parity bit to determine if there is an MBE. When an MBE is detected an MBE signal is activated. In some embodiments, an MBE flag may be set based on the MBE signal being active.

公开(公告)号：US11625343B2

公开(公告)日：2023-04-11

申请号：US17318219

申请日：2021-05-12

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/28 ,  G06F13/40

Abstract: Memory systems with a communications bus (and associated systems, devices, and methods) are disclosed herein. In one embodiment, a memory device includes an input/output terminal separate from data terminals of the memory device. The input/output terminal can be operably connected to a memory controller via a communications bus. The memory device can be configured to initiate a communication with the memory controller by outputting a signal via the input/output terminal and/or over the communications bus. The memory device can be configured to output the signal in accordance with a clock signal that is different from a second clock signal used to output or receive data signals via the data terminals. In some embodiments, the memory device is configured to initiate communications over the communication bus only when it possesses a communication token. The communication token can be transferred between memory devices operably connected to the communications bus.

公开(公告)号：US11568918B2

公开(公告)日：2023-01-31

申请号：US17170616

申请日：2021-02-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi ,  Raghukiran Sreeramaneni

IPC: G11C11/408 ,  G11C11/406 ,  G11C15/04 ,  G11C11/16 ,  G11C11/4074

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for analog row access rate determination. Accesses to different row addresses may be tracked by storing one or more received addresses in a slice of stack. Each slice includes an accumulator circuit which provides a voltage based on charge on a capacitor. When a row address is received, it may be compared to the row addresses stored in the stack, and if there is a match, the charge on the capacitor in the associated accumulator circuit is increased. Each slice may also include a voltage to time (VtoT) circuit which may be used to identify the highest of the voltages provided by the accumulator circuits. The row address stored in the slide with the highest voltage may be refreshed.