METHOD OF REDUCING CONTAMINATION BY PROVIDING AN ETCH STOP LAYER AT THE SUBSTRATE EDGE
    121.
    发明申请
    METHOD OF REDUCING CONTAMINATION BY PROVIDING AN ETCH STOP LAYER AT THE SUBSTRATE EDGE 有权
    通过在基板边缘处提供蚀刻停止层来减少污染的方法

    公开(公告)号:US20070155133A1

    公开(公告)日:2007-07-05

    申请号:US11531793

    申请日:2006-09-14

    IPC分类号: H01L21/00

    摘要: By providing an etch stop layer selectively at the bevel, at least one additional wet chemical bevel etch process may be performed prior to or during the formation of a metallization layer without affecting the substrate material. Hence, the dielectric material, especially the low-k dielectric material, may be reliably removed from the bevel prior to the formation of any barrier and metal layers. The etch stop layer may be formed at an early manufacturing stage so that a bevel etch process may be performed at any desired stage of the formation of circuit elements.

    摘要翻译: 通过在斜面上选择性地设置蚀刻停止层,可以在形成金属化层之前或期间执行至少一个附加的湿化学斜面蚀刻工艺,而不影响衬底材料。 因此,在形成任何阻挡层和金属层之前,电介质材料,特别是低k电介质材料可以从斜面被可靠地移除。 蚀刻停止层可以在早期制造阶段形成,从而可以在形成电路元件的任何期望阶段执行斜面蚀刻工艺。

    TECHNIQUE FOR INCREASING ADHESION OF METALLIZATION LAYERS BY PROVIDING DUMMY VIAS
    123.
    发明申请
    TECHNIQUE FOR INCREASING ADHESION OF METALLIZATION LAYERS BY PROVIDING DUMMY VIAS 有权
    通过提供DUMMY VIAS来增加金属化层粘合的技术

    公开(公告)号:US20070123009A1

    公开(公告)日:2007-05-31

    申请号:US11470024

    申请日:2006-09-05

    IPC分类号: H01L21/20

    摘要: By providing dummy vias below electrically non-functional metal regions, the risk for metal delamination in subsequent processes may be significantly reduced. Moreover, in some embodiments, the mechanical strength of the resulting metallization layers may be even more enhanced by providing dummy metal regions, which may act as anchors for an overlying non-functional metal region. In addition, dummy vias may also be provided in combination with electrically functional metal lines and regions, thereby also enhancing the mechanical stability and the electrical performance thereof.

    摘要翻译: 通过在电气非功能金属区域之下提供虚拟通孔,可以显着降低后续工艺中金属分层的风险。 而且,在一些实施例中,所得到的金属化层的机械强度甚至可以通过提供虚拟金属区域来进一步增强,虚拟金属区域可以用作覆盖的非功能性金属区域的锚点。 此外,还可以与电功能金属线和区域组合提供虚拟通孔,从而也增强机械稳定性及其电性能。

    Climate control system and motor actuator therefor
    124.
    发明授权
    Climate control system and motor actuator therefor 失效
    气候控制系统及电动执行机构

    公开(公告)号:US06844692B1

    公开(公告)日:2005-01-18

    申请号:US10645515

    申请日:2003-08-22

    摘要: A motor actuator (52) of a climate control system (37) includes an specialized electric motor (62) with a motor housing enclosing an encoder ring (104) on a motor shaft (77) having a plurality of opposite encoder-segment sets with encoder brushes (96a-b) on the housing wiping the encoder ring and thereby forming an encoder circuit through opposite segments of the encoder-segment sets. The electric motor further includes power and encoder terminals (98a-b and 100a-b) positioned externally of the motor housing with at least one power terminal being electrically coupled to one of the power brushes and at least one encoder terminal being electrically coupled to one of the encoder brushes. A control head (58) of the system includes a continuity pulse counter (72) coupled to the at least one encoder terminal for creating pulses representative of impedance in the encoder circuit and, therefore, movement of the motor shaft and a damper (40) linked thereto.

    摘要翻译: 气候控制系统(37)的电动机致动器(52)包括专用电动机(62),其具有电动机壳体,该电动机壳体包围电动机轴(77)上的编码器环(104),电动机轴具有多个相对的编码器段组, 编码器电刷(96a-b)在外壳上擦拭编码器环,从而通过编码器段组的相对部分形成编码器电路。 电动机还包括位于电动机壳体外部的动力和编码器端子(98a-b和100a-b),其中至少一个电力端子电耦合到电力电刷之一,并且至少一个编码器端子电耦合到一个 的编码器刷子​​。 系统的控制头(58)包括连接到至少一个编码器端的连续脉冲计数器(72),用于产生代表编码器电路中的阻抗的脉冲,因此电动机轴和阻尼器(40)的运动, 与之相关联。

    Polyamide graft copolymers
    125.
    发明授权
    Polyamide graft copolymers 失效
    聚酰胺接枝共聚物

    公开(公告)号:US06538073B1

    公开(公告)日:2003-03-25

    申请号:US09604281

    申请日:2000-06-26

    IPC分类号: C08L7700

    摘要: A graft copolymer suitable as a blend component or as a hot-melt adhesive, which contains the following monomer units: a) from 0.5 to 25% by weight, based on the graft copolymer, of a polyamine having at least 11 nitrogen atoms and a number-average molar mass Mn of at least 500 g/mol; and b) an equimolar combination of diamine and dicarboxylic acid as polyamide-forming monomers.

    摘要翻译: 适合作为共混组分或热熔粘合剂的接枝共聚物,其包含以下单体单元:a)基于接枝共聚物,0.5至25重量%的具有至少11个氮原子的多胺和 数均摩尔质量Mn为至少500g / mol; 和b)作为形成聚酰胺的单体的二胺和二羧酸的等摩尔组合。

    Free-flowing transparent polyamide molding composition
    126.
    发明授权
    Free-flowing transparent polyamide molding composition 有权
    自由流动的透明聚酰胺成型组合物

    公开(公告)号:US06407182B1

    公开(公告)日:2002-06-18

    申请号:US09768286

    申请日:2001-01-25

    IPC分类号: C08L7700

    CPC分类号: C08L77/00

    摘要: Transparent molding compositions are prepared by blending from 50 to 99 parts by weight of a transparent polyamide, and from 1 to 50 parts by weight of a graft copolymer, such that the sum of the parts by weight of the transparent polyamide and the graft copolymer is 100. The graft copolymer is prepared by reacting from 0.5 to 25% by weight, based on the graft copolymer, of a branched polyamine having at least 4 nitrogen atoms and having a number average molecular weight Mn of at least 146 g/mol, with polyamide-forming monomers selected from the group consisting of lactams, &ohgr;-aminocarboxylic acids, equimolar combinations of diamine and dicarboxylic acid, and combinations thereof.

    摘要翻译: 通过将50至99重量份的透明聚酰胺和1至50重量份的接枝共聚物共混来制备透明模塑组合物,使得透明聚酰胺和接枝共聚物的重量份之和为 接枝共聚物通过基于接枝共聚物使0.5至25重量%的具有至少4个氮原子并具有至少146g / mol数均分子量Mn的支链多胺与 选自内酰胺,ω-氨基羧酸,二胺和二羧酸的等摩尔组合的聚酰胺形成单体及其组合。

    Processes for forming integrated circuits and integrated circuits formed thereby
    128.
    发明授权
    Processes for forming integrated circuits and integrated circuits formed thereby 有权
    用于形成集成电路和由此形成的集成电路的工艺

    公开(公告)号:US08906801B2

    公开(公告)日:2014-12-09

    申请号:US13417491

    申请日:2012-03-12

    摘要: Processes for forming integrated circuits and integrated circuits formed thereby are provided in which a first dielectric layer including a first dielectric material is formed on an underlying substrate. A first etch mask having at least two patterned recesses is patterned over the first dielectric layer. At least one first-level via is etched in the first dielectric layer through one patterned recess in the first etch mask with a first etchant, and the first-level via is filled with electrically-conductive material. A second dielectric layer including a second dielectric material is formed over the first dielectric layer. A second etch mask having patterned recesses corresponding to the patterned recesses of the first etch mask is patterned over the second dielectric layer. Second-level vias are etched in the second dielectric layer through the patterned recesses in the second etch mask with a second etchant and exposed to the first etchant.

    摘要翻译: 提供了用于形成由此形成的集成电路和集成电路的工艺,其中包括第一介电材料的第一介电层形成在下面的基板上。 具有至少两个图案化凹槽的第一蚀刻掩模在第一介电层上图案化。 在第一蚀刻掩模中通过第一蚀刻掩模中的一个图案化凹槽在第一介电层中蚀刻至少一个第一级通孔,并且第一级通孔用导电材料填充。 在第一电介质层上形成包括第二电介质材料的第二电介质层。 具有对应于第一蚀刻掩模的图案化凹部的图案化凹坑的第二蚀刻掩模在第二介电层上图案化。 第二电介质层通过具有第二蚀刻剂的第二蚀刻掩模中的图案化凹槽蚀刻在第二介电层中并暴露于第一蚀刻剂。

    Method of forming metal gates and metal contacts in a common fill process
    129.
    发明授权
    Method of forming metal gates and metal contacts in a common fill process 有权
    在普通填充过程中形成金属栅极和金属触点的方法

    公开(公告)号:US08685807B2

    公开(公告)日:2014-04-01

    申请号:US13100798

    申请日:2011-05-04

    IPC分类号: H01L21/336

    摘要: The method described herein involves a method of forming metal gates and metal contacts in a common fill process. The method may involve forming a gate structure comprising a sacrificial gate electrode material, forming at least one conductive contact opening in a layer of insulating material positioned adjacent the gate structure, removing the sacrificial gate electrode material to thereby define a gate electrode opening, and performing a common deposition process to fill the conductive contact opening and the gate electrode opening with a conductive fill material.

    摘要翻译: 本文描述的方法涉及在公共填充过程中形成金属栅极和金属触点的方法。 该方法可以包括形成包括牺牲栅电极材料的栅极结构,在邻近栅极结构定位的绝缘材料层中形成至少一个导电接触开口,去除牺牲栅电极材料,从而限定栅电极开口,并执行 用于用导电填充材料填充导电接触开口和栅电极开口的公共沉积工艺。

    Optimized buffer placement based on timing and capacitance assertions
    130.
    发明授权
    Optimized buffer placement based on timing and capacitance assertions 失效
    基于定时和电容断言优化的缓冲放置

    公开(公告)号:US08566774B2

    公开(公告)日:2013-10-22

    申请号:US13293351

    申请日:2011-11-10

    IPC分类号: G06F9/455 G06F17/50

    摘要: A method is provided for optimized buffer placement based on timing and capacitance assertions in a functional chip unit including a single source and multiple macros, each having a sink. Placement of the source and macros with the sinks is pre-designed and buffers are placed in branches connecting the source with the multiple sinks. The method includes: calculating an estimated slack for each branch based on cycle reach, calculating a minimum slack for each branch, arranging branches according to the calculated slack to evaluate at least one most critical branch, inserting decoupling buffers in all branches except the most critical branch(es) and placing decoupling buffers close to the source, globally routing the most critical branch(es) and fixing slew conditions within this branch, globally routing at least one subsequent branch as arranged according to the calculated slack and fixing slew conditions within this branch(es), and routing all remaining branches.

    摘要翻译: 提供了一种基于包括单个源和多个宏的功能芯片单元中的定时和电容断言来优化缓冲器放置的方法,每个宏具有接收器。 源和宏与接收器的放置是预先设计的,并且缓冲器被放置在连接源与多个接收器的分支中。 该方法包括:基于周期到达计算每个分支的估计松弛,计算每个分支的最小松弛,根据计算的松弛来布置分支以评估至少一个最关键分支,在除最大关键点之外的所有分支中插入去耦缓冲器 分支,并将去耦缓冲区放置在源附近,全局路由最重要的分支和固定此分支中的转换条件,全局路由至少一个后续分支,根据计算的松弛和固定转换条件排列 分支,并路由所有剩余的分支。