公开(公告)号：US20200251486A1

公开(公告)日：2020-08-06

申请号：US16268183

申请日：2019-02-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori TSUTSUMI ,  Manabu KAKAZU ,  Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/11529 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: A three-dimensional memory device includes a vertical semiconductor channel surrounding a vertical dielectric core. Laterally extending dielectric pegs structurally support the vertical semiconductor channel and the vertical dielectric core. The vertical semiconductor channel may be a single crystalline semiconductor channel.

公开(公告)号：US20200251374A1

公开(公告)日：2020-08-06

申请号：US16263086

申请日：2019-01-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA ,  Yao-Sheng LEE ,  Jian CHEN

IPC: H01L21/687 ,  H01L23/00 ,  H01L23/522 ,  H01L27/11582 ,  H01L27/11565

Abstract: A first semiconductor die and a second semiconductor die can be bonded in a manner that enhances alignment of bonding pads. Non-uniform deformation of a first wafer including first semiconductor dies can be compensated for by forming a patterned stress-generating film on a backside of the first wafer. Metallic bump portions can be formed on concave surfaces of metallic bonding pads by a selective metal deposition process to reduce gaps between pairs of bonded metallic bonding pads. Pad-to-pad pitch can be adjusted on a semiconductor die to match the pad-to-pad pitch of another semiconductor die employing a tilt-shift operation in a lithographic exposure tool. A chuck configured to provide non-uniform displacement across a wafer can be employed to hold a wafer in a contoured shape for bonding with another wafer in a matching contoured position. Independently height-controlled pins can be employed to hold a wafer in a non-planar configuration.

公开(公告)号：US20200235116A1

公开(公告)日：2020-07-23

申请号：US16251854

申请日：2019-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chun GE ,  Yanli ZHANG ,  Fei ZHOU ,  Raghuveer S. MAKALA

IPC: H01L27/11568 ,  H01L27/1159 ,  H01L29/423 ,  H01L29/78 ,  H01L29/792 ,  H01L29/51 ,  H01L21/28

Abstract: A combination of an alternating stack and a memory opening fill structure is provided over a substrate. The alternating stack includes insulating layers and electrically conductive layers. The memory opening fill structure vertically extends through the alternating stack, and includes a memory film, a vertical semiconductor channel, and a core structure comprising a core material. A phase change material is employed for the core material. A volume expansion is induced in in the core material by performing an anneal process that induces a microstructural change within the core material. The volume expansion in the core material induces a lateral compressive strain and a vertical tensile strain within the vertical semiconductor channel. The vertical tensile strain enhances charge mobility in the vertical semiconductor channel, and increases the on-current of the vertical semiconductor channel.

公开(公告)号：US20180374866A1

公开(公告)日：2018-12-27

申请号：US15633131

申请日：2017-06-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. MAKALA ,  Senaka Krishna KANAKAMEDALA ,  Yanli ZHANG ,  Yao-Sheng LEE

IPC: H01L27/11582 ,  H01L29/51 ,  H01L29/423 ,  H01L27/11575 ,  H01L27/11565 ,  H01L29/08 ,  H01L21/28 ,  H01L21/311

CPC classification number: H01L27/11582 ,  H01L21/31122 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L29/0847 ,  H01L29/40117 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517

Abstract: A strap level sacrificial layer and an alternating stack of insulating layers and spacer material layers are formed over a substrate. An array of memory stack structures is formed through the alternating stack and the strap level sacrificial layer. Each memory film in the memory stack structures includes a metal oxide blocking dielectric. After formation of a source cavity by removal of the strap level sacrificial layer, an atomic layer etch process can be employed to remove portions of the metal oxide blocking dielectrics at the level of the source cavity. Outer sidewalls of semiconductor channels in the memory stack structures are exposed by additional etch processes, and a source strap layer is selectively deposited in the source cavity in contact with the semiconductor channel. If the spacer material layers are sacrificial material layers, all volumes of the sacrificial material layers can be replaced with the electrically conductive layers.

公开(公告)号：US20180097009A1

公开(公告)日：2018-04-05

申请号：US15286063

申请日：2016-10-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli ZHANG ,  Johann ALSMEIER ,  Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA ,  Rahul SHARANGPANI ,  James KAI

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/7926

Abstract: A layer stack including an alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of memory stack structures, backside trenches are formed through the layer stack. The sacrificial material layers are replaced with electrically conductive layers. Drain select level dielectric isolation structures are formed through drain select level of the stack after formation of the electrically conductive layers. The drain select level dielectric isolation structures laterally separate portions of conductive layers that are employed as drain select level gate electrodes for the memory stack structures.

公开(公告)号：US20180033646A1

公开(公告)日：2018-02-01

申请号：US15730045

申请日：2017-10-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Fumitaka AMANO ,  Raghuveer S. MAKALA ,  Adarsh RAJASHEKHAR ,  Fei ZHOU

IPC: H01L21/443 ,  H01L21/3065 ,  H01L27/108 ,  H01L21/311 ,  H01L27/06 ,  H01L21/768 ,  H01L21/441 ,  H01L29/49 ,  H01L27/105

CPC classification number: H01L27/11563 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/441 ,  H01L21/443 ,  H01L21/76871 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/11534 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/495 ,  H01L29/4975

Abstract: Word lines for a three-dimensional memory device can be formed by forming a stack of alternating layers comprising insulating layers and sacrificial material layers and memory stack structures vertically extending therethrough. Backside recesses are formed by removing the sacrificial material layers through a backside via trench. A metal silicide layer and metal portion are formed in the backside recesses to form the word lines including a metal portion, a metal silicide layer, and optionally, a silicon-containing layer.