公开(公告)号：US20170062620A1

公开(公告)日：2017-03-02

申请号：US15244041

申请日：2016-08-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masashi TSUBUKU ,  Masashi OOTA ,  Akihisa SHIMOMURA ,  Yasumasa YAMANE

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78696

Abstract: A novel oxide semiconductor is provided. An oxide semiconductor contains In, an element M (M represents Al, Ga, Y, or Sn), and Zn. The oxide semiconductor has little characteristics variation and structure change and has high electron mobility in the case where the atomic ratio of In to M and Zn in the oxide semiconductor ranges from 4:2:3 to 4:2:4.1 or is a neighborhood thereof.

Abstract translation: 提供了一种新型氧化物半导体。 氧化物半导体含有In，元素M（M表示Al，Ga，Y或Sn）和Zn。 在氧化物半导体中的In与M和Zn的原子比为4：2：3〜4：2：4.1的情况下，氧化物半导体具有很小的特性变化和结构变化，并且具有高的电子迁移率，或者是其附近 。

公开(公告)号：US20170040459A1

公开(公告)日：2017-02-09

申请号：US15296432

申请日：2016-10-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masashi TSUBUKU ,  Kosei NODA ,  Kouhei TOYOTAKA ,  Kazunori WATANABE ,  Hikaru HARADA

IPC: H01L29/786 ,  H01L29/423 ,  H01L27/12

CPC classification number: H01L29/7869 ,  G06F15/76 ,  H01L27/10805 ,  H01L27/10873 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1112 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L28/60 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/78696

Abstract: An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.

Abstract translation: 目的是提供一种存储器件，其包括可通过具有低截止电流的薄膜晶体管无故障地操作的存储元件。 提供了一种存储器件，其中包括至少一个包括氧化物半导体层的薄膜晶体管的存储元件被布置为矩阵。 包括氧化物半导体层的薄膜晶体管具有高场效应迁移率和低截止电流，因此可以有利地操作而没有问题。 此外，可以降低功耗。 由于存储器件和像素可以形成在一个衬底上，所以这种存储器件在包括氧化物半导体层的薄膜晶体管被设置在显示器件的像素中的情况下是特别有效的。

公开(公告)号：US20170018631A1

公开(公告)日：2017-01-19

申请号：US15276993

申请日：2016-09-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Akihisa SHIMOMURA ,  Yasumasa YAMANE ,  Yuhei SATO ,  Tetsuhiro TANAKA ,  Masashi TSUBUKU ,  Toshihiko TAKEUCHI ,  Ryo TOKUMARU ,  Mitsuhiro ICHIJO ,  Satoshi TORIUMI ,  Takashi OHTSUKI ,  Toshiya ENDO

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: A change in electrical characteristics is suppressed and reliability in a semiconductor device using a transistor including an oxide semiconductor is improved. The semiconductor device includes an oxide semiconductor film over an insulating surface, an antioxidant film over the insulating surface and the oxide semiconductor film, a pair of electrodes in contact with the antioxidant film, a gate insulating film over the pair of electrodes, and a gate electrode which is over the gate insulating film and overlaps with the oxide semiconductor film. In the antioxidant film, a width of a region overlapping with the pair of electrodes is longer than a width of a region not overlapping with the pair of electrodes.

Abstract translation: 抑制了电特性的变化，并且提高了使用包括氧化物半导体的晶体管的半导体器件的可靠性。 半导体器件包括绝缘表面上的氧化物半导体膜，绝缘表面上的抗氧化膜和氧化物半导体膜，与抗氧化膜接触的一对电极，一对电极上的栅极绝缘膜，以及栅极 电极，其在栅极绝缘膜上方并与氧化物半导体膜重叠。 在抗氧化剂膜中，与该对电极重叠的区域的宽度比不与该对电极重叠的区域的宽度长。

公开(公告)号：US20160336459A1

公开(公告)日：2016-11-17

申请号：US15219764

申请日：2016-07-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takafumi MIZOGUCHI ,  Kojiro SHIRAISHI ,  Masashi TSUBUKU

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/24

CPC classification number: H01L29/78606 ,  H01L21/764 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/24 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object is to provide a method for manufacturing a semiconductor device without exposing a specific layer to moisture or the like at all. A thin film element is manufactured in such a manner that a first film, a second film, and a third film are stacked in this order; a resist mask is formed over the third film; a mask layer is formed by etching the third film with the use of the resist mask; the resist mask is removed; a second layer and a first layer are formed by performing dry etching on the second film and the first film with the use of the mask layer; a fourth film is formed to cover at least the second layer and the first layer; and sidewall layers are formed to cover at least the entire side surfaces of the first layer by performing etch back on the fourth film.

Abstract translation: 本发明的目的是提供一种制造半导体器件的方法，而不会将特定层暴露于湿气等。 制造薄膜元件，使得第一膜，第二膜和第三膜按此顺序堆叠; 在第三膜上形成抗蚀剂掩模; 通过使用抗蚀剂掩模蚀刻第三膜来形成掩模层; 去除抗蚀剂掩模; 通过使用掩模层对第二膜和第一膜进行干蚀刻来形成第二层和第一层; 形成第四膜至少覆盖第二层和第一层; 并且通过在第四膜上进行回蚀而形成侧壁层以至少覆盖第一层的整个侧表面。

公开(公告)号：US20160329359A1

公开(公告)日：2016-11-10

申请号：US15217177

申请日：2016-07-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masashi TSUBUKU ,  Shuhei YOSHITOMI ,  Takahiro TSUJI ,  Miyuki HOSOBA ,  Junichiro SAKATA ,  Hiroyuki TOMATSU ,  Masahiko HAYAKAWA

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L27/1262 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02595 ,  H01L21/02631 ,  H01L21/02667 ,  H01L27/1248 ,  H01L27/127 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/7869

Abstract: It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured.

公开(公告)号：US20160240694A1

公开(公告)日：2016-08-18

申请号：US15137613

申请日：2016-04-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Hiroki OHARA ,  Tatsuya HONDA ,  Takatsugu OMATA ,  Yusuke NONAKA ,  Masahiro TAKAHASHI ,  Akiharu MIYANAGA

IPC: H01L29/786 ,  H01L29/24

CPC classification number: H01L29/78696 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/247 ,  H01L29/7869 ,  H01L29/78693

Abstract: An oxide semiconductor film which has more stable electric conductivity is provided. The oxide semiconductor film comprises a crystalline region. The oxide semiconductor film has a first peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.4 nm−1 and less than or equal to 0.7 nm−1 in a region where a magnitude of a scattering vector is greater than or equal to 3.3 nm−1 and less than or equal to 4.1 nm−1. The oxide semiconductor film has a second peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.45 nm−1 and less than or equal to 1.4 nm−1 in a region where a magnitude of a scattering vector is greater than or equal to 5.5 nm−1 and less than or equal to 7.1 nm−1.

公开(公告)号：US20160217830A1

公开(公告)日：2016-07-28

申请号：US14996635

申请日：2016-01-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masashi TSUBUKU ,  Masashi FUJITA

IPC: G11C5/10

CPC classification number: G11C14/0045 ,  G11C11/401 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/79

Abstract: Provided is a highly reliable semiconductor device, a semiconductor device with a reduced circuit area, a memory element having favorable characteristics, a highly reliable memory element, or a memory element with increased storage capacity per unit volume. A semiconductor device includes a capacitor and a switching element. The capacitor includes a first electrode, a second electrode, and a dielectric. The dielectric is positioned between the first electrode and the second electrode. The switching element includes a first terminal and a second terminal. The first terminal is electrically connected to the first electrode. The following steps are sequentially performed: a first step of turning on the switching element in a first period, a second step of turning off the switching element in a second period, and a third step of turning on the switching element in a third period.

Abstract translation: 提供了一种高度可靠的半导体器件，具有减小的电路面积的半导体器件，具有有利特性的存储元件，高度可靠的存储元件或具有每单位体积的存储容量增加的存储元件。 半导体器件包括电容器和开关元件。 电容器包括第一电极，第二电极和电介质。 电介质位于第一电极和第二电极之间。 开关元件包括第一端子和第二端子。 第一端子电连接到第一电极。 顺序执行以下步骤：在第一周期中接通开关元件的第一步骤，在第二时段中断开开关元件的第二步骤，以及在第三时间段内接通开关元件的第三步骤。

公开(公告)号：US20160118418A1

公开(公告)日：2016-04-28

申请号：US14989927

申请日：2016-01-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masashi TSUBUKU ,  Kosei NODA ,  Kouhei TOYOTAKA ,  Kazunori WATANABE ,  Hikaru HARADA

IPC: H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/7869 ,  G06F15/76 ,  H01L27/10805 ,  H01L27/10873 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1112 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L28/60 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/78696

Abstract: An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.

Abstract translation: 目的是提供一种存储器件，其包括可通过具有低截止电流的薄膜晶体管无故障地操作的存储元件。 提供了一种存储器件，其中包括至少一个包括氧化物半导体层的薄膜晶体管的存储元件被布置为矩阵。 包括氧化物半导体层的薄膜晶体管具有高场效应迁移率和低截止电流，因此可以有利地操作而没有问题。 此外，可以降低功耗。 由于存储器件和像素可以形成在一个衬底上，所以这种存储器件在包括氧化物半导体层的薄膜晶体管被设置在显示器件的像素中的情况下是特别有效的。

公开(公告)号：US20150069393A1

公开(公告)日：2015-03-12

申请号：US14547285

申请日：2014-11-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masashi TSUBUKU ,  Takayuki INOUE ,  Suzunosuke HIRAISHI ,  Erumu KIKUCHI ,  Hiromichi GODO ,  Shuhei YOSHITOMI ,  Koki INOUE ,  Akiharu MIYANAGA ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L29/40

CPC classification number: H01L29/7869 ,  H01L29/408

Abstract: Manufactured is a transistor including an oxide semiconductor layer, a source electrode layer and a drain electrode layer overlapping with part of the oxide semiconductor layer, a gate insulating layer overlapping with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode overlapping with part of the oxide semiconductor layer with the gate insulating layer provided therebetween, wherein, after the oxide semiconductor layer which is to be a channel formation region is irradiated with light and the light irradiation is stopped, a relaxation time of carriers in photoresponse characteristics of the oxide semiconductor layer has at least two kinds of modes: τ1 and τ2, τ1

Abstract translation: 制造的是包括与氧化物半导体层的一部分重叠的氧化物半导体层，源极电极层和漏极电极层，与氧化物半导体层重叠的栅极绝缘层，源极电极层和漏极电极层的晶体管， 以及与所述氧化物半导体层的与氧化物半导体层的一部分重叠的栅电极，其间设置有栅极绝缘层，其中，在作为沟道形成区域的氧化物半导体层被照射光并停止光照射之后，弛豫时间 氧化物半导体层的光响应特性中的载流子具有至少两种模式：τ1和τ2，τ1<τ2，τ2为300秒以下。 此外，制造包括晶体管的半导体器件。

公开(公告)号：US20150044818A1

公开(公告)日：2015-02-12

申请号：US14521710

申请日：2014-10-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masashi TSUBUKU ,  Shuhei YOSHITOMI ,  Takahiro TSUJI ,  Miyuki HOSOBA ,  Junichiro SAKATA ,  Hiroyuki TOMATSU ,  Masahiko HAYAKAWA

IPC: H01L27/12 ,  H01L29/66

CPC classification number: H01L27/1262 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02595 ,  H01L21/02631 ,  H01L21/02667 ,  H01L27/1248 ,  H01L27/127 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/7869

Abstract: It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured.

Abstract translation: 本发明的目的是提供一种包括氧化物半导体膜的薄膜晶体管的结构的制造方法，其中形成沟道的阈值电压为正且尽可能接近0V。 形成保护绝缘层以覆盖包括通过第一热处理脱水或脱氢的氧化物半导体层的薄膜晶体管，以及在比第一热处理低的温度下进行第二热处理，其中， 重复多次温度的降低，由此，在不影响通道长度的情况下，包含氧化物半导体层的薄膜晶体管，其中形成沟道的阈值电压为正且尽可能接近0V，可以 制造。