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    Wiring Layer and Manufacturing Method Therefor
    1.
    发明申请
    Wiring Layer and Manufacturing Method Therefor 有权
    接线层及其制造方法

    公开(公告)号：US20160099259A1

    公开(公告)日：2016-04-07

    申请号：US14870912

    申请日：2015-09-30

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yutaka Okazaki ,  Tomoaki MORIWAKA ,  Shinya SASAGAWA ,  Takashi OHTSUKI

    IPC: H01L27/12 ,  H01L21/768

    CPC classification number: H01L27/124 ,  H01L21/76849 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/1255 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78609 ,  H01L29/78648 ,  H01L29/78654 ,  H01L29/7869

    Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.

    Abstract translation: 提供具有低功耗的小型化半导体器件。 制造布线层的方法包括以下步骤：在第一绝缘体上形成第二绝缘体; 在所述第二绝缘体上形成第三绝缘体; 在第三绝缘体中形成开口，使其到达第二绝缘体; 在第三绝缘体和开口中形成第一导体; 在所述第一导体上形成第二导体; 并且在形成第二导体之后，进行抛光处理以去除第三绝缘体的顶表面上方的第一和第二导体的部分。 第一导体的端部处于低于或等于开口顶部水平的水平。 第二导体的顶表面处于低于或等于第一导体末端的水平面。

    PHOTOELECTRIC CONVERSION DEVICE AND MANUFACTURING METHOD THEREOF
    3.
    发明申请
    PHOTOELECTRIC CONVERSION DEVICE AND MANUFACTURING METHOD THEREOF 有权
    光电转换装置及其制造方法

    公开(公告)号：US20150053264A1

    公开(公告)日：2015-02-26

    申请号：US14514552

    申请日：2014-10-15

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Sho KATO ,  Yoshikazu HIURA ,  Akihisa SHIMOMURA ,  Takashi OHTSUKI ,  Satoshi TORIUMI ,  Yasuyuki ARAI

    IPC: H01L31/077 ,  H01L31/0376

    CPC classification number: H01L31/077 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/075 ,  H01L31/1804 ,  H01L31/20 ,  Y02E10/547 ,  Y02E10/548 ,  Y02P70/521

    Abstract: An object is to increase conversion efficiency of a photoelectric conversion device without increase in the manufacturing steps. The photoelectric conversion device includes a first semiconductor layer formed using a single crystal semiconductor having one conductivity type which is formed over a supporting substrate, a buffer layer including a single crystal region and an amorphous region, a second semiconductor layer which includes a single crystal region and an amorphous region and is provided over the butler layer, and a third semiconductor layer having a conductivity type opposite to the one conductivity type, which is provided over the second semiconductor layer. A proportion of the single crystal region is higher than that of the amorphous region on the first semiconductor layer side in the second semiconductor layer, and the proportion of the amorphous region is higher than that of the single crystal region on the third semiconductor layer side.

    Abstract translation: 目的在于提高光电转换装置的转换效率，而不增加制造步骤。 光电转换装置包括使用在支撑基板上形成的具有一种导电类型的单晶半导体形成的第一半导体层，包括单晶区域和非晶区域的缓冲层，包括单晶区域的第二半导体层 和非晶区域，并且设置在管状层上方，以及设置在第二半导体层上的具有与一种导电类型相反的导电类型的第三半导体层。 单晶区域的比例高于第二半导体层中的第一半导体层侧的非晶区域的比例，并且非晶区域的比例高于第三半导体层侧的单晶区域的比例。

    Wiring Layer and Manufacturing Method Therefor
    4.
    发明申请
    Wiring Layer and Manufacturing Method Therefor 审中-公开

    公开(公告)号：US20200258914A1

    公开(公告)日：2020-08-13

    申请号：US16863291

    申请日：2020-04-30

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yutaka Okazaki ,  Tomoaki MORIWAKA ,  Shinya SASAGAWA ,  Takashi OHTSUKI

    IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L21/768

    Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.

    WIRING LAYER AND MANUFACTURING METHOD THEREFOR
    5.
    发明申请
    WIRING LAYER AND MANUFACTURING METHOD THEREFOR 审中-公开

    公开(公告)号：US20190355751A1

    公开(公告)日：2019-11-21

    申请号：US16423884

    申请日：2019-05-28

    Applicant: Semiconductor Energy Laboratory Co., Ltd

    Inventor： Yutaka OKAZAKI ,  Tomoaki Moriwaka ,  Shinya SASAGAWA ,  Takashi OHTSUKI

    IPC: H01L27/12 ,  H01L21/768 ,  H01L29/786 ,  H01L29/66

    Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.

    Wiring Layer And Manufacturing Method Therefor
    7.
    发明申请
    Wiring Layer And Manufacturing Method Therefor 有权

    公开(公告)号：US20220189996A1

    公开(公告)日：2022-06-16

    申请号：US17557355

    申请日：2021-12-21

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yutaka Okazaki ,  Tomoaki MORIWAKA ,  Shinya SASAGAWA ,  Takashi OHTSUKI

    IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L21/768

    Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.

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