公开(公告)号：US09152661B1

公开(公告)日：2015-10-06

申请号：US13278785

申请日：2011-10-21

Applicant: Satish Sathe ,  Rajendra Marulkar ,  Sagar Vaishampayan

Inventor： Satish Sathe ,  Rajendra Marulkar ,  Sagar Vaishampayan

IPC: G06F7/00 ,  G06F17/30

CPC classification number: G06F17/3033 ,  G06F17/30982

Abstract: System and method for searching a data structure are disclosed. The method includes providing a data structure that includes a plurality of data entries stored in an external random access memory (RAM) and a portion of the data structure is stored in an internal cache memory, performing one or more hash functions on each entry of the data structure to generate an encoding that maps to a location in the external RAM, maintaining a count of encodings that map to the location in the external RAM, receiving a search string, performing the one or more hash functions on the search string to generate an index to the count of encodings, and searching the data structure in accordance with the count of encodings stored in the internal cache memory and in the external RAM.

Abstract translation: 公开了一种用于搜索数据结构的系统和方法。 该方法包括提供包括存储在外部随机存取存储器（RAM）中的多个数据条目的数据结构，并且该数据结构的一部分存储在内部高速缓冲存储器中，对该数据结构的每个条目执行一个或多个散列函数 数据结构以生成映射到外部RAM中的位置的编码，保持映射到外部RAM中的位置的编码计数，接收搜索字符串，在搜索字符串上执行一个或多个散列函数以生成 索引到编码的计数，并且根据存储在内部高速缓冲存储器和外部RAM中的编码的计数来搜索数据结构。

公开(公告)号：US09088357B2

公开(公告)日：2015-07-21

申请号：US13661490

申请日：2012-10-26

Applicant: APPLIED MICRO CIRCUITS CORPORATION ,  VOLEX PLC

Inventor： Benoit Sevigny ,  Ezra Gold

IPC: H04B10/00 ,  H04B10/11 ,  H04N5/225 ,  G01B11/14 ,  G02B6/42 ,  H04B10/114 ,  G01B11/26

CPC classification number: H04B10/11 ,  G01B11/14 ,  G01B11/26 ,  G02B6/4219 ,  H04B10/114 ,  H04N5/225

Abstract: Methods and systems for facilitating alignment of optical systems and optoelectronic systems are disclosed here. The methods and systems include passively detecting images, determining relative positions of components and aligning components. An imaging component can detect images and determine relative positions and repositioning instructions.

Abstract translation: 这里公开了用于促进光学系统和光电子系统的对准的方法和系统。 方法和系统包括被动地检测图像，确定部件和对准部件的相对位置。 成像组件可以检测图像并确定相对位置和重新定位指令。

公开(公告)号：US08964452B2

公开(公告)日：2015-02-24

申请号：US13726800

申请日：2012-12-26

Applicant: Applied Micro Circuits Corporation

Inventor： Jason T. Su ,  Bin Liang

IPC: G11C11/00 ,  G11C7/10 ,  G11C11/419

CPC classification number: G11C7/1096 ,  G11C11/419

Abstract: Providing for improved write processes of a semiconductor memory are disclosed herein. By way of example, a programmable write assist can be provided that includes partially discharging a supply voltage applied to a memory cell. Partially discharging the supply voltage can improve write speeds to the memory cell, as well as improve reliability of the write process. A write assist circuit can cause the discharging in response to a resistance-modulated signal. Moreover, the resistance-modulated signal can be configured to control an amount or speed of the discharging of the supply voltage. Further, modulation control can be provided to mitigate discharging of the supply voltage beyond a target level, to reduce data loss in a target data cell or an adjacent data cell.

Abstract translation: 本文公开了提供半导体存储器的改进的写入处理。 作为示例，可以提供可编程写入辅助，其包括部分地放电施加到存储器单元的电源电压。 部分放电电源可以提高对存储单元的写入速度，并提高写入过程的可靠性。 写辅助电路可以响应于电阻调制信号而引起放电。 此外，电阻调制信号可以被配置为控制电源电压的放电的量或速度。 此外，可以提供调制控制以减轻电源电压超出目标电平的放电，以减少目标数据单元或相邻数据单元中的数据丢失。

公开(公告)号：US20150049847A1

公开(公告)日：2015-02-19

申请号：US13965375

申请日：2013-08-13

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Moshe Malkin

IPC: H04B1/12 ,  H04B1/38

CPC classification number: H03H17/0202 ,  H03H17/0213

Abstract: Techniques for fast filtering for a transceiver are presented. A multidimensional filter processor component (MDFPC) can perform configurations and adaptations of multiple digital filters of a transceiver. The MDFPC can treat multiple, separate filters of a transceiver as a single larger multidimensional filter, and jointly update the multiple filters in a single adaptation operation instead of performing multiple adaptation operations on multiple filters. To facilitate multidimensional filter adaptation, the MDFPC can manage respective cross-correlations associated with the inputs of the filters. The MDFPC can facilitate multidimensional filter adaptation by performing multidimensional filter adaptation in the frequency domain, wherein the adaptation can be performed in parallel for multiple frequency sub-channels. For each frequency sub-channel, the MDFPC can perform a filter adaptation, wherein respective filter adaptation matrices can be generated for respective frequency sub-channels to perform the update to facilitate managing different cross-correlations associated with different frequency sub-channels.

Abstract translation: 介绍了收发器快速滤波技术。 多维滤波处理器组件（MDFPC）可以执行收发器的多个数字滤波器的配置和调整。 MDFPC可以将收发器的多个单独的滤波器作为单个更大的多维滤波器来处理，并且在单个适配操作中联合更新多个滤波器，而不是在多个滤波器上执行多个适配操作。 为了便于多维滤波器适配，MDFPC可以管理与滤波器的输入相关联的相互交叉相关。 MDFPC可以通过在频域中执行多维滤波器适配来促进多维滤波器适应，其中可以针对多个频率子信道并行执行自适应。 对于每个频率子信道，MDFPC可以执行滤波器适配，其中可以为各个频率子信道生成各自的滤波器适配矩阵以执行更新以便于管理与不同频率子信道相关联的不同交叉相关。

公开(公告)号：US08897118B1

公开(公告)日：2014-11-25

申请号：US13023641

申请日：2011-02-09

Applicant: Shi Cheng ,  Ravi Narasimhan

Inventor： Shi Cheng ,  Ravi Narasimhan

IPC: H04J11/00

CPC classification number: H04W56/0035

Abstract: A method is provided for Single Carrier-Frequency-Division Multiple Access (SC-FDMA) Physical Uplink Control Channel (PUCCH) format 1/1a/1b detection in a wireless communications receiver. The receiver accepts a plurality of multicarrier signals transmitted simultaneously from a plurality of transmitters, with overlapping carrier frequencies. For each multicarrier signal, a single tap measurement of time delay is performed using a Direction of Arrival (DoA) technique. In response to the single tap measurements, PUCCH 1/1a/1b format signals are detected. Prior to performing the single tap measurements, the multicarrier signals are decorrelated in the time domain, using corresponding orthogonal code covers. Subsequent to the single tap measurements, each multicarrier signal is decorrelated in the frequency domain, using a corresponding cyclic shift. Subsequent to decorrelating the multicarrier signals in the frequency domain, a Generalized Likelihood Ratio Test (GLRT) is performed for each decorrelated multicarrier signal.

Abstract translation: 在无线通信接收机中提供用于单载波 - 频分多址（SC-FDMA）物理上行链路控制信道（PUCCH）格式1 / 1a / 1b检测的方法。 接收机接受多个发射机同时发射的多载波信号，具有重叠的载波频率。 对于每个多载波信号，使用到达方向（DoA）技术来执行时间延迟的单次测量。 响应于单抽头测量，检测PUCCH 1 / 1a / 1b格式信号。 在执行单抽头测量之前，多载波信号在时域中被解相关，使用对应的正交码覆盖。 在单抽头测量之后，使用相应的循环移位，在频域中将每个多载波信号解相关。 在对频域中的多载波信号进行去相关之后，对每个去相关的多载波信号执行广义似然比测试（GLRT）。

公开(公告)号：US08829995B2

公开(公告)日：2014-09-09

申请号：US14021834

申请日：2013-09-09

Applicant: Applied Micro Circuits Corporation

Inventor： Hanan Cohen

IPC: H03F3/45

CPC classification number: H03G3/3078 ,  H03F3/45183 ,  H03F3/45197 ,  H03F2200/408 ,  H03F2200/435 ,  H03F2200/447 ,  H03F2203/45296 ,  H03F2203/45298 ,  H03F2203/45374 ,  H03F2203/45631 ,  H03F2203/45686 ,  H03F2203/45702

Abstract: A method is provided for process, voltage, temperature (PVT) stable transfer function calibration in a differential amplifier. The gain resistors of a differential amplifier are initially selected to achieve a flat amplitude transfer function in the first frequency band. After calibration, the degeneration capacitor is connected and tuned until a peaked amplitude transfer function is measured, which is resistant to variations in PVT. As an alternative, the degeneration capacitor is not disconnected during initial calibration. Then, the gain resistors and the degeneration capacitor values are selectively adjusted until the first peaked amplitude transfer function is obtained. The peaked amplitude transfer function remains even more stable to variations in PVT than the flat amplitude calibration method.

Abstract translation: 提供了差分放大器中的过程，电压，温度（PVT）稳定传递函数校准的方法。 最初选择差分放大器的增益电阻以在第一频带中实现平坦的幅度传递函数。 校准后，连接并调谐退化电容，直到测量出峰值的幅度传递函数，这抵消了PVT的变化。 作为替代方案，在初始校准期间，退化电容器不断开。 然后，选择性地调节增益电阻器和退化电容器值，直到获得第一峰值幅度传递函数。 峰值幅度传递函数对于PVT的变化比平坦幅度校准方法保持更稳定。

公开(公告)号：US08806140B1

公开(公告)日：2014-08-12

申请号：US12784542

申请日：2010-05-21

Applicant: Waseem Saify Kraipak ,  George Bendak

Inventor： Waseem Saify Kraipak ,  George Bendak

IPC: G06F12/00

CPC classification number: G11C7/20 ,  G06F1/3275 ,  G06F12/0862 ,  G06F2212/2022 ,  G11C2029/0401 ,  Y02D10/13 ,  Y02D10/14

Abstract: A system and method are provided for using a system-on-chip (SoC) memory manager to optimize the use of off-chip memory modules. A SoC memory controller receives a request for a first data block, subsequent to shutting the first memory down, and determines that the first data block is stored in the first memory. A SoC memory switching core uses a memory map to translate the first data block address in the first memory module to a first data block address in the second memory module. If the first data block is present in an on-SoC cache, the first data block is supplied on the SoC data bus from the cache. Then, the cache is loaded with a plurality of data blocks from a corresponding plurality of addresses in the second memory module, associated with the first data block address.

Abstract translation: 提供了一种用于使用片上系统（SoC）存储器管理器来优化片外存储器模块的使用的系统和方法。 SoC存储器控制器在关闭第一存储器之后接收对第一数据块的请求，并且确定第一数据块被存储在第一存储器中。 SoC存储器切换核心使用存储器映射将第一存储器模块中的第一数据块地址转换为第二存储器模块中的第一数据块地址。 如果第一数据块存在于SoC高速缓存中，则第一数据块从高速缓存提供给SoC数据总线。 然后，从第二存储器模块中与第一数据块地址相关联的相应多个地址中加载多个数据块。

公开(公告)号：US08767757B1

公开(公告)日：2014-07-01

申请号：US13396711

申请日：2012-02-15

Applicant: Keyur Chudgar ,  Satish Sathe

Inventor： Keyur Chudgar ,  Satish Sathe

IPC: H04L12/28

CPC classification number: H04L45/745 ,  H04L45/66

Abstract: A method is provided for forwarding packets. Using a control plane state machine, addresses in a packet header are examined to derive a pointer value. The pointer value is used to access entries in a result database to identify routing information, a buffer pool ID associated with a location in memory, and a queue ID. A direct memory access (DMA) engine writes the packet into the memory location in response to the first message including the buffer pool ID. The QM prepares a second message associated with the packet, the second message including the routing information, the memory allocation in the buffer pool ID, and the queue ID. An operating system reads the second message, reads the packet from the memory allocation, modifies the packet header using the routing information, and writes the modified packet back into the memory allocation.

Abstract translation: 提供了转发数据包的方法。 使用控制平面状态机，检查分组报头中的地址以导出指针值。 指针值用于访问结果数据库中的条目以识别路由信息，与存储器中的位置相关联的缓冲池ID和队列ID。 直接存储器访问（DMA）引擎响应于包括缓冲池ID的第一消息将数据包写入存储器位置。 QM准备与分组相关联的第二消息，第二消息包括路由信息，缓冲池ID中的内存分配和队列ID。 操作系统读取第二个消息，从存储器分配中读取数据包，使用路由信息修改数据包头，并将修改后的数据包写入存储器分配。

公开(公告)号：US08761209B1

公开(公告)日：2014-06-24

申请号：US13285562

申请日：2011-10-31

Applicant: Matthew Brown ,  Dimitrios Giannakopoulos

Inventor： Matthew Brown ,  Dimitrios Giannakopoulos

IPC: H04J3/02 ,  H04L12/54 ,  H04L29/06

CPC classification number: H04L12/413

Abstract: An Ethernet physical layer (PHY) module is provided with a method for transceiving between a 10GBASE-R client interface and a 100G attachment interface. On each of ten client interface logical lanes a 10GBASE-R signal is accepted. Each 10GBASE-R logical lane is demultiplexed into two 5 gigabit per second (Gbps) pseudo 100GBASE-R logical lanes, creating a total of twenty pseudo 100GBASE-R logical lanes. The pseudo 100GBASE-R logical lanes are arranged into n groups of 20/n pseudo 100GBASE-R logical lanes. Further, the pseudo 100GBASE-R logical lanes from each group are arranged into a 100G attachment logical lane. Finally, a 100G attachment logical lane is transmitted at an attachment interface on each of n physical lanes. In the reverse direction, each of n physical lanes accepts a 100G attachment logical lane at the attachment interface, and a de-aggregation process supplies a 10GBASE-R signal on each of ten client interface logical lanes.

Abstract translation: 以太网物理层（PHY）模块提供了一种用于在10GBASE-R客户端接口和100G附件接口之间进行收发的方法。 在10个客户端界面逻辑通道中的每一个上接受10GBASE-R信号。 每个10GBASE-R逻辑通道被解复用为两个5千兆位/秒（Gbps）伪100GBASE-R逻辑通道，共创建了20个伪100GBASE-R逻辑通道。 伪100GBASE-R逻辑通道被排列成n组20 / n个伪100GBASE-R逻辑通道。 此外，来自每组的伪100GBASE-R逻辑通道被排列成100G附件逻辑通道。 最后，在n个物理通道中的每一个上的附着接口上发送100G附件逻辑通道。 在相反的方向上，n个物理通道中的每一个在附接接口处接受100G的连接逻辑通道，并且去聚合处理在十个客户端接口逻辑通道中的每一个上提供10GBASE-R信号。

公开(公告)号：US20140147945A1

公开(公告)日：2014-05-29

申请号：US14171339

申请日：2014-02-03

Applicant: VOLEX PLC ,  APPLIED MICRO CIRCUITS CORPORATION

Inventor： Subhash Roy ,  Igor Zhovnirovsky ,  Sergey Vinogradov

IPC: H01L31/02 ,  H01L21/66

CPC classification number: G01J1/44 ,  H01L22/14 ,  H01L27/1446 ,  H01L31/00 ,  H01L31/02019 ,  H01L31/022408 ,  H01L31/03529 ,  H01L31/105 ,  H01L31/108 ,  H01L31/1085 ,  H01L2924/0002 ,  Y02E10/50 ,  H01L2924/00

Abstract: A photodetector with a bandwidth-tuned cell structure is provided. The photodetector is fabricated from a semiconductor substrate that is heavily doped with a first dopant. A plurality of adjoining cavities is formed in the semiconductor substrate having shared cell walls. A semiconductor well is formed in each cavity, moderately doped with a second dopant opposite in polarity to the first dopant. A layer of oxide is grown overlying the semiconductor wells and an annealing process is performed. Then, metal pillars are formed that extend into each semiconductor well having a central axis aligned with an optical path. A first electrode is connected to the metal pillar of each cell, and a second electrode connected to the semiconductor substrate. The capacitance between the first and second electrodes decreases in response to forming an increased number of semiconductor wells with a reduced diameter, and forming metal pillars with a reduced diameter.

Abstract translation: 提供具有带宽调谐单元结构的光电检测器。 光电检测器由重掺杂第一掺杂剂的半导体衬底制成。 在具有共享单元壁的半导体衬底中形成多个邻接的空腔。 在每个空腔中形成半导体阱，中等掺杂有与第一掺杂剂极性相反的第二掺杂剂。 生长覆盖在半导体阱上的一层氧化物，并进行退火处理。 然后，形成延伸到具有与光路对准的中心轴的每个半导体阱中的金属柱。 第一电极连接到每个电池的金属柱，以及连接到半导体衬底的第二电极。 响应于形成具有减小的直径的增加数量的半导体阱并且形成直径减小的金属柱，第一和第二电极之间的电容减小。