公开(公告)号：US20110180851A1

公开(公告)日：2011-07-28

申请号：US13038190

申请日：2011-03-01

Applicant: Brian S. Doyle ,  Been-Yih Jin ,  Jack T. Kavalieros ,  Suman Datta ,  Justin K. Brask ,  Robert S. Chau

Inventor： Brian S. Doyle ,  Been-Yih Jin ,  Jack T. Kavalieros ,  Suman Datta ,  Justin K. Brask ,  Robert S. Chau

IPC: H01L29/772

CPC classification number: H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.

Abstract translation: 这里描述了利用具有单功函数的栅电极材料的器件，用于pMOS和nMOS晶体管，其中晶体管阈值电压的幅度由半导体带工程和由此制成的制品修改。 本文进一步描述的是制造由互补（pMOS和nMOS）晶体管形成的器件的方法，该晶体管具有被设计成能够实现低阈值电压的带隙的半导体沟道区。

公开(公告)号：US20110156005A1

公开(公告)日：2011-06-30

申请号：US12655468

申请日：2009-12-30

Applicant: Ravi Pillarisetty ,  Been-Yih Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

Inventor： Ravi Pillarisetty ,  Been-Yih Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

IPC: H01L29/772

CPC classification number: H01L27/092 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7782

Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

Abstract translation: 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅极电介质材料允许使用高k值栅极电介质。

公开(公告)号：US20110147847A1

公开(公告)日：2011-06-23

申请号：US12653971

申请日：2009-12-21

Applicant: Stephen M. Cea ,  Martin D. Giles ,  Kelin Kuhn ,  Jack T. Kavalieros ,  Markus Kuhn

Inventor： Stephen M. Cea ,  Martin D. Giles ,  Kelin Kuhn ,  Jack T. Kavalieros ,  Markus Kuhn

IPC: H01L29/78 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L29/66795 ,  H01L29/7842

Abstract: The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming isolation structures in strained semiconductor bodies of non-planar transistors while maintaining strain in the semiconductor bodies.

Abstract translation: 本公开涉及制造微电子器件的领域。 在至少一个实施例中，本公开涉及在保持半导体本体中的应变的同时在非平面晶体管的应变半导体本体中形成隔离结构。

公开(公告)号：US07791063B2

公开(公告)日：2010-09-07

申请号：US11847780

申请日：2007-08-30

Applicant: Mantu K. Hudait ,  Suman Datta ,  Jack T. Kavalieros ,  Peter G. Tolchinsky

Inventor： Mantu K. Hudait ,  Suman Datta ,  Jack T. Kavalieros ,  Peter G. Tolchinsky

IPC: H01L29/205 ,  H01L21/20

CPC classification number: H01L29/7782 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/02505 ,  H01L21/02546 ,  H01L21/02573 ,  H01L21/0262 ,  H01L29/267 ,  H01L29/66431

Abstract: The present disclosure provides an apparatus and method for implementing a high hole mobility p-channel Germanium (“Ge”) transistor structure on a Silicon (“Si”) substrate. One exemplary apparatus may include a buffer layer including a GaAs nucleation layer, a first GaAs buffer layer, and a second GaAs buffer layer. The exemplary apparatus may further include a bottom barrier on the second GaAs buffer layer and having a band gap greater than 1.1 eV, a Ge active channel layer on the bottom barrier and having a valence band offset relative to the bottom barrier that is greater than 0.3 eV, and an AlAs top barrier on the Ge active channel layer wherein the AlAs top barrier has a band gap greater than 1.1 eV. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

Abstract translation: 本公开提供了一种在硅（“Si”）衬底上实现高空穴迁移率p沟道锗（“Ge”）晶体管结构的装置和方法。 一个示例性装置可以包括包括GaAs成核层，第一GaAs缓冲层和第二GaAs缓冲层的缓冲层。 该示例性装置还可以包括第二GaAs缓冲层上的底部阻挡层，并具有大于1.1eV的带隙，底部势垒上的Ge活性通道层，并且相对于底部势垒的价带偏移大于0.3 eV和Ge活性通道层上的AlAs顶部势垒，其中AlAs顶部势垒具有大于1.1eV的带隙。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

公开(公告)号：US20100219396A1

公开(公告)日：2010-09-02

申请号：US12715034

申请日：2010-03-01

Applicant: Been-Yih Jin ,  Jack T. Kavalieros ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

Inventor： Been-Yih Jin ,  Jack T. Kavalieros ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

IPC: H01L29/12 ,  H01L21/20

CPC classification number: H01L29/161 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/7782 ,  H01L29/78

Abstract: A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.

Abstract translation: 制造量子阱器件的方法包括在量子阱的δ层的侧面上形成扩散阻挡层，以将掺杂剂限制在量子阱中。

公开(公告)号：US20100193771A1

公开(公告)日：2010-08-05

申请号：US12756989

申请日：2010-04-08

Applicant: Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

Inventor： Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

IPC: H01L29/772

CPC classification number: H01L29/66431 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/152 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848 ,  H01L29/802

Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

Abstract translation: 所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。 沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变 顶部阻挡层和量子阱的底部缓冲层。

公开(公告)号：US20100163970A1

公开(公告)日：2010-07-01

申请号：US12317966

申请日：2008-12-31

Applicant: Titash Rakshit ,  Stephen M. Cea ,  Jack T. Kavalieros ,  Ravi Pillarisetty

Inventor： Titash Rakshit ,  Stephen M. Cea ,  Jack T. Kavalieros ,  Ravi Pillarisetty

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A trigate device having an extended metal gate electrode comprises a semiconductor body having a top surface and opposing sidewalls formed on a substrate, an isolation layer formed on the substrate and around the semiconductor body, wherein a portion of the semiconductor body remains exposed above the isolation layer, and a gate stack formed on the top surface and opposing sidewalls of the semiconductor body, wherein the gate stack extends a depth into the isolation layer, thereby causing a bottom surface of the gate stack to be below a top surface of the isolation layer.

Abstract translation: 具有延伸的金属栅电极的触发装置包括半导体本体，其具有形成在基板上的顶表面和相对的侧壁，形成在基板上并围绕半导体主体的隔离层，其中半导体主体的一部分保持暴露在隔离物的上方 层，以及形成在半导体主体的顶表面和相对侧壁上的栅极堆叠，其中栅极堆叠将深度延伸到隔离层中，从而使栅极堆叠的底表面在隔离层的顶表面下方 。

公开(公告)号：US20100163847A1

公开(公告)日：2010-07-01

申请号：US12347268

申请日：2008-12-31

Applicant: Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

Inventor： Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

IPC: H01L29/12 ,  H01L21/336 ,  H01L21/18 ,  H01L21/203

CPC classification number: H01L29/66431 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/152 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848 ,  H01L29/802

Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

公开(公告)号：US07700470B2

公开(公告)日：2010-04-20

申请号：US11525765

申请日：2006-09-22

Applicant: Willy Rachmady ,  Uday Shah ,  Jack T. Kavalieros ,  Brian S. Doyle

Inventor： Willy Rachmady ,  Uday Shah ,  Jack T. Kavalieros ,  Brian S. Doyle

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/823842 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785

Abstract: Embodiments of an apparatus and methods for providing a workfunction metal gate electrode on a substrate with doped metal oxide semiconductor structures are generally described herein. Other embodiments may be described and claimed.

Abstract translation: 在此通常描述用于在具有掺杂金属氧化物半导体结构的衬底上提供功函数金属栅电极的装置和方法的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US07642603B2

公开(公告)日：2010-01-05

申请号：US11823892

申请日：2007-06-29

Applicant: Suman Datta ,  Titash Rakshit ,  Jack T. Kavalieros ,  Brian S. Doyle

Inventor： Suman Datta ,  Titash Rakshit ,  Jack T. Kavalieros ,  Brian S. Doyle

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

Abstract: In one embodiment of the invention, a non-planar transistor includes a gate electrode and multiple fins. A trench contact is coupled to the fins. The contact bottom is formed above the substrate and does not directly contact the substrate. The contact bottom is higher than the gate top.

Abstract translation: 在本发明的一个实施例中，非平面晶体管包括栅电极和多个散热片。 沟槽接触件连接到鳍片。 接触底部形成在衬底之上并且不直接接触衬底。 触点底部高于门顶。