INTEGRATED STACKED POWER AMPLIFIER AND RF SWITCH ARCHITECTURE
    131.
    发明申请
    INTEGRATED STACKED POWER AMPLIFIER AND RF SWITCH ARCHITECTURE 有权
    集成堆叠功率放大器和射频开关架构

    公开(公告)号:US20130314163A1

    公开(公告)日:2013-11-28

    申请号:US13900077

    申请日:2013-05-22

    Inventor: Julio Costa

    Abstract: Combination circuitry includes a relatively small preamplifier and includes hybrid circuitry. The hybrid circuitry is configured to perform mode switching while also performing some amplification, thus allowing the relatively small preamplifier to be smaller than a conventional power amplifier. In one embodiment, the hybrid circuitry includes first series portion configured to amplify when ON, a first shunt portion, a second series portion configured to amplify when ON, and a second shunt portion. The first series portion may include: a first transistor; a first variable impedance in communication with a gate of the first transistor, wherein the first variable impedance is configured to receive a first transistor control signal; a second transistor in series with the first transistor; and a second variable impedance in communication with a gate of the second transistor, wherein second variable impedance is configured to receive a second transistor control signal.

    Abstract translation: 组合电路包括相对小的前置放大器并且包括混合电路。 混合电路被配置为执行模式切换,同时还执行一些放大,从而允许相对小的前置放大器小于常规功率放大器。 在一个实施例中,混合电路包括第一串联部分,其被配置为当ON时放大,第一分流部分,被配置为在ON时被放大的第二串联部分和第二分流部分。 第一串联部分可以包括:第一晶体管; 与所述第一晶体管的栅极通信的第一可变阻抗,其中所述第一可变阻抗被配置为接收第一晶体管控制信号; 与第一晶体管串联的第二晶体管; 以及与第二晶体管的栅极通信的第二可变阻抗,其中第二可变阻抗被配置为接收第二晶体管控制信号。

    EXTRACTING CLOCK INFORMATION FROM A SERIAL COMMUNICATIONS BUS FOR USE IN RF COMMUNICATIONS CIRCUITRY
    132.
    发明申请
    EXTRACTING CLOCK INFORMATION FROM A SERIAL COMMUNICATIONS BUS FOR USE IN RF COMMUNICATIONS CIRCUITRY 有权
    从RF通信电路中使用的串行通信总线提取时钟信息

    公开(公告)号:US20130294554A1

    公开(公告)日:2013-11-07

    申请号:US13937307

    申请日:2013-07-09

    CPC classification number: H04L7/04 G06F13/385 H04J3/0685

    Abstract: The present disclosure relates to RF front-end (RFFE) circuitry that includes multiple RFFE circuits, each of which may be provided by a separate integrated circuit (IC), front-end module, or both. As such, the RFFE circuits may be connected to one another using an RFFE serial communications bus. Further, one or more of the RFFE circuits may need an accurate clock source for analog-to-digital conversion (ADC), digital-to-analog conversion (DAC), calibration, sensor measurements, or the like. Instead of including an integral clock source circuit or receiving a separate external clock signal, an RFFE circuit may extract clock information from the RFFE serial communications bus to provide one or more clock signals. The clock information may be associated with one or more serial communications commands via the RFFE serial communications bus, may be associated with alternate functionality of the RFFE serial communications bus, or both.

    Abstract translation: 本公开涉及包括多个RFFE电路的RF前端(RFFE)电路,每个RFFE电路可以由单独的集成电路(IC),前端模块或两者提供。 因此,RFFE电路可以使用RFFE串行通信总线彼此连接。 此外,一个或多个RFFE电路可能需要用于模数转换(ADC),数模转换(DAC),校准,传感器测量等的精确时钟源。 RFFE电路不是包含集成时钟源电路或者接收单独的外部时钟信号,而是可以从RFFE串行通信总线提取时钟信息以提供一个或多个时钟信号。 时钟信息可以经由RFFE串行通信总线与一个或多个串行通信命令相关联,可以与RFFE串行通信总线或两者的备用功能相关联。

    MULTI-MODE POWER AMPLIFIER ARCHITECTURE
    134.
    发明申请
    MULTI-MODE POWER AMPLIFIER ARCHITECTURE 有权
    多模式功率放大器架构

    公开(公告)号:US20130250820A1

    公开(公告)日:2013-09-26

    申请号:US13887965

    申请日:2013-05-06

    Inventor: Nadim Khlat

    CPC classification number: H04L5/18 H04B1/0057 H04L5/14

    Abstract: Radio frequency (RF) circuitry, which includes a time division duplex (TDD)/frequency division duplex (FDD) driver stage, a TDD final stage, an FDD final stage, and power directing circuitry, is disclosed. The power directing circuitry is coupled between the TDD/FDD driver stage and the TDD final stage, and is further coupled between the TDD/FDD driver stage and the FDD final stage.

    Abstract translation: 公开了包括时分双工(TDD)/频分双工(FDD)驱动器级,TDD最终级,FDD最后级和功率定向电路的射频(RF)电路。 功率引导电路耦合在TDD / FDD驱动级和TDD最终级之间,并且进一步耦合在TDD / FDD驱动级和FDD最后级之间。

    CARRIER AGGREGATION FRONT END ARCHITECTURE
    135.
    发明申请
    CARRIER AGGREGATION FRONT END ARCHITECTURE 有权
    承运人聚集前端建筑

    公开(公告)号:US20130250819A1

    公开(公告)日:2013-09-26

    申请号:US13848393

    申请日:2013-03-21

    Abstract: Radio frequency (RF) front end circuitry includes a notch diplexer. The notch diplexer includes a high pass filter coupled between a high band port and an antenna port, and a low pass notch filter coupled between a low band port and the antenna port. The high pass filter is adapted to receive a high band receive signal having a high band carrier frequency at the antenna port, and pass the high band receive signal to the high band port. The low pass notch filter is adapted to receive a low band transmit signal having a low band carrier frequency at the low band port, and attenuate distortion in the low band transmit signal about a notch stop band before passing the low band transmit signal to the antenna port. According to one embodiment, the notch stop band includes the high band carrier frequency.

    Abstract translation: 射频(RF)前端电路包括一个切口双工器。 陷波分波器包括耦合在高频带端口和天线端口之间的高通滤波器以及耦合在低频带端口和天线端口之间的低通陷波滤波器。 高通滤波器适于在天线端口处接收具有高频带载波频率的高频带接收信号,并将高频带接收信号传送到高频带端口。 低通陷波滤波器适于在低频带端口接收具有低频带载波频率的低频带发射信号,并且在通过低频带发射信号到天线之前衰减低频带发射信号关于陷波阻挡带的失真 港口。 根据一个实施例,陷波阻挡带包括高频带载波频率。

    MULTIPLE PORT RF SWITCH ESD PROTECTION USING SINGLE PROTECTION STRUCTURE
    137.
    发明申请
    MULTIPLE PORT RF SWITCH ESD PROTECTION USING SINGLE PROTECTION STRUCTURE 有权
    多端口RF开关使用单一保护结构的ESD保护

    公开(公告)号:US20130215808A1

    公开(公告)日:2013-08-22

    申请号:US13849834

    申请日:2013-03-25

    CPC classification number: H02H9/045 H01L27/0274 H01L27/0292 H02H9/046

    Abstract: Antenna switching circuitry comprises a plurality of communication ports, an antenna port, a plurality of switches, and an ESD protection device. The plurality of switches are adapted to selectively couple one or more of the communication ports to the antenna port in order to transmit or receive a signal. The ESD protection device is coupled between one of the plurality of communication ports and ground, and is adapted to form a substantially low impedance path to ground during an ESD event. Upon the occurrence of an ESD event, a received electrostatic charge passes through one or more of the plurality of switches to the ESD protection device, where it is safely diverted to ground. By using only one ESD protection device, desensitization of the antenna switching circuitry due to the parasitic loading of the ESD protection device is avoided. Further, the area of the antenna switching circuitry is minimized.

    Abstract translation: 天线切换电路包括多个通信端口,天线端口,多个开关和ESD保护装置。 多个开关适于选择性地将一个或多个通信端口耦合到天线端口以便发送或接收信号。 ESD保护装置耦合在多个通信端口中的一个和地之间,并且适于在ESD事件期间形成基本上低的接地路径。 在发生ESD事件时,接收的静电电荷通过多个开关中的一个或多个开关到ESD保护装置,在那里它被安全地转移到地面。 通过仅使用一个ESD保护装置,避免了由于ESD保护装置的寄生负载导致的天线开关电路的脱敏。 此外,天线切换电路的面积被最小化。

    SHUNT SWITCH AT COMMON PORT TO REDUCE HOT SWITCHING
    138.
    发明申请
    SHUNT SWITCH AT COMMON PORT TO REDUCE HOT SWITCHING 有权
    在通用端口的分流开关减少热切换

    公开(公告)号:US20130207714A1

    公开(公告)日:2013-08-15

    申请号:US13764324

    申请日:2013-02-11

    Abstract: Pilot switch circuitry grounds a hot node (an injection node) of a microelectromechanical system (MEMS) switch to reduce or eliminate arcing between a cantilever contact and a terminal contact when the MEMS switch is opened or closed. The pilot switch circuitry grounds the hot node prior to, during, and after the cantilever contact and terminal contact of the MEMS come into contact with one another (when the MEMS switch is closed). Additionally, the pilot switch circuitry grounds the hot node prior to, during, and after the cantilever contact and terminal contact of the MEMS disengage from one another (when the MEMS switch is opened).

    Abstract translation: 导向开关电路将微机电系统(MEMS)开关的热节点(注入节点)接地,以在MEMS开关打开或关闭时减少或消除悬臂触点和端子触点之间的电弧。 在MEMS悬臂接触之前,期间和之后,导频开关电路将热节点接地,并且MEMS的端子接触彼此接触(当MEMS开关闭合时)。 此外,导频开关电路在MEMS的彼此脱离接合之前,之中和之后,以及MEMS的彼此脱离接合(当MEMS开关断开时)接地。

    TUNABLE DUPLEXER ARCHITECTURE
    139.
    发明申请
    TUNABLE DUPLEXER ARCHITECTURE 有权
    TUNABLE双机架构

    公开(公告)号:US20130201880A1

    公开(公告)日:2013-08-08

    申请号:US13760159

    申请日:2013-02-06

    CPC classification number: H04L5/14 H03H7/48 H04B1/44 H04B1/525 H04L25/03878

    Abstract: A tunable radio frequency (RF) duplexer is disclosed. The tunable RF duplexer includes a first hybrid coupler, a second hybrid coupler, and an RF filter circuit. The first hybrid coupler is operable to split an RF receive input signal into first and second RF quadrature hybrid receive signals (QHRSs). The first hybrid coupler is also operable to split an RF transmission input signal into first and second RF quadrature hybrid transmission signals (QHTSs). The RF filter circuit is operable to pass the first and second RF QHRSs to the second hybrid coupler and to reflect the first and second RF QHTSs back to the first hybrid coupler. Additionally, the second hybrid coupler is configured to combine the first and second RF QHRSs into an RF receive output signal, while the first hybrid coupler is configured to combine the first and second RF QHTSs into an RF transmission output signal.

    Abstract translation: 公开了一种可调谐射频(RF)双工器。 可调RF双工器包括第一混合耦合器,第二混合耦合器和RF滤波器电路。 第一混合耦合器可操作以将RF接收输入信号分成第一和第二RF正交混合接收信号(QHRS)。 第一混合耦合器还可操作以将RF传输输入信号分成第一和第二RF正交混合传输信号(QHTS)。 RF滤波器电路可操作以将第一和第二RF QHRS传递到第二混合耦合器并将第一和第二RF QHTS反射回第一混合耦合器。 此外,第二混合耦合器被配置为将第一和第二RF QHRS组合成RF接收输出信号,而第一混合耦合器被配置为将第一和第二RF QHTS组合成RF发射输出信号。

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