公开(公告)号：US11990547B2

公开(公告)日：2024-05-21

申请号：US17033897

申请日：2020-09-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yu Chen ,  Bo-Lin Huang ,  Jhong-Yi Huang ,  Keng-Jen Lin ,  Yu-Shu Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/16

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L29/16

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming recesses adjacent to two sides of the gate structure, forming a buffer layer in the recesses, forming a first linear bulk layer on the buffer layer, forming a second linear bulk layer on the first linear bulk layer, forming a bulk layer on the second linear bulk layer, and forming a cap layer on the bulk layer.

公开(公告)号：US11990546B2

公开(公告)日：2024-05-21

申请号：US18120995

申请日：2023-03-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Hua Yang ,  Chih-Chien Chang ,  Shen-De Wang

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/7816 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, a first oxide layer, a field plate, and a second oxide layer. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure respectively. The first oxide layer includes a first portion disposed between the gate structure and the semiconductor substrate and a second portion disposed between the gate structure and the drain region. The field plate is partly disposed above the gate structure and partly disposed above the second portion of the first oxide layer. The second oxide layer includes a first portion disposed between the field plate and the gate structure and a second portion disposed between the field plate and the second portion of the first oxide layer.

公开(公告)号：US11990346B2

公开(公告)日：2024-05-21

申请号：US17391075

申请日：2021-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chuan-Chang Wu ,  Zhen Wu ,  Hsuan-Hsu Chen ,  Chun-Lung Chen

IPC: H01L21/311 ,  H01L21/3213 ,  H01L29/66

CPC classification number: H01L21/32134 ,  H01L29/66545

Abstract: A method for a clean procedure during manufacturing a semiconductor device, includes: providing a patterned sacrificial gate structure including a gate dielectric and a sacrificial layer; wherein the patterned sacrificial gate structure is embedded in a dielectric layer and an upper surface of the sacrificial layer is exposed; performing a first etching process to remove the sacrificial layer; and performing a hydrophilic treatment and a hydrophobic treatment to remove a residue of the sacrificial layer.

公开(公告)号：US20240162208A1

公开(公告)日：2024-05-16

申请号：US18077192

申请日：2022-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Chih-Wei Chang ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chung-Yi Chiu

IPC: H01L25/16 ,  H01L29/20 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L29/47 ,  H01L29/66 ,  H01L29/778 ,  H01L31/0224 ,  H01L31/0304 ,  H01L31/0352 ,  H01L31/18 ,  H03H3/08 ,  H03H9/02

CPC classification number: H01L25/167 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/454 ,  H01L29/475 ,  H01L29/66462 ,  H01L29/7786 ,  H01L31/022408 ,  H01L31/03044 ,  H01L31/035236 ,  H01L31/1856 ,  H03H3/08 ,  H03H9/02976

Abstract: A structure with a photodiode, an HEMT and an SAW device includes a photodiode and an HEMT. The photodiode includes a first electrode and a second electrode. The first electrode contacts a P-type III-V semiconductor layer. The second electrode contacts an N-type III-V semiconductor layer. The HEMT includes a P-type gate disposed on an active layer. A gate electrode is disposed on the P-type gate. Two source/drain electrodes are respectively disposed at two sides of the P-type gate. Schottky contact is between the first electrode and the P-type III-V semiconductor layer, and between the gate electrode and the P-type gate. Ohmic contact is between the second electrode and the first N-type III-V semiconductor layer, and between one of the two source/drain electrodes and the active layer and between the other one of two source/drain electrodes and the active layer.

公开(公告)号：US20240154027A1

公开(公告)日：2024-05-09

申请号：US18413045

申请日：2024-01-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Han Wu ,  Kai-Kuen Chang ,  Ping-Hung Chiang

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/66674 ,  H01L29/7801

Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first drift region, a gate structure, a first sub gate structure, a first spacer structure, a second spacer structure, and a first insulation structure. The first drift region is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate and separated from the first sub gate structure. The first sub gate structure and the first insulation structure are disposed on the first drift region. The first spacer structure is disposed on a sidewall of the gate structure. The second spacer structure is disposed on a sidewall of the first sub gate structure. At least a part of the first insulation structure is located between the first spacer structure and the second spacer structure. The first insulation structure is directly connected with the first drift region located between the first spacer structure and the second spacer structure.

公开(公告)号：US11977335B2

公开(公告)日：2024-05-07

申请号：US17353582

申请日：2021-06-21

Applicant: United Microelectronics Corp.

Inventor： Min Cheng Yang ,  Wei Cyuan Lo ,  Yung-Feng Cheng

IPC: G03F7/00 ,  G03F1/36 ,  G03F1/70

CPC classification number: G03F7/70466 ,  G03F1/36 ,  G03F1/70 ,  G03F7/70475

Abstract: A pattern decomposition method including following steps is provided. A target pattern is provided, wherein the target pattern includes first patterns and second patterns alternately arranged, and the width of the second pattern is greater than the width of the first pattern. Each of the second patterns is decomposed into a third pattern and a fourth pattern, wherein the third pattern and the fourth pattern have an overlapping portion, and a pattern formed by overlapping the third pattern and the fourth pattern is the same as the second pattern. The third patterns and the first pattern adjacent to the fourth pattern are designated as first photomask patterns of a first photomask. The fourth patterns and the first pattern adjacent to the third pattern are designated as second photomask patterns of a second photomask.

公开(公告)号：US20240147683A1

公开(公告)日：2024-05-02

申请号：US17994381

申请日：2022-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Wei Yeh ,  Chang-Hung Chen

IPC: H01L27/11

CPC classification number: H01L27/1104

Abstract: The invention provides a layout pattern of static random access memory, which comprises a plurality of fin structures on a substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate. The transistors include a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2) and a second pull-down transistor (PD2), a first access transistor (PG1), a second access transistor (PG2), a first read port transistor (RPD) and a second read port transistor (RPG). The gate structure of the first read port transistor (RPD) is connected to the gate structure of the first pull-down transistor (PD1), wherein a drain of the first pull-down transistor (PD1) is connected to a first voltage source Vss1, and a drain of the first read port transistor (RPD) is connected to a second voltage source Vss2.

公开(公告)号：US20240138144A1

公开(公告)日：2024-04-25

申请号：US17994009

申请日：2022-11-25

Applicant: United Microelectronics Corp.

Inventor： Yu-Jen Yeh

IPC: H01L29/76 ,  H01L29/423

CPC classification number: H01L27/11553 ,  H01L29/42328

Abstract: Provided are a flash memory and a manufacturing method thereof. The flash memory includes a floating gate disposed in a substrate, a first, a second and a third dielectric layers, a source region, a drain region, an erase gate on the second dielectric layer, and a select gate. The first dielectric layer is disposed between the floating gate and the substrate. The second dielectric layer covers the exposed surface of the floating gate. The source region is disposed in the substrate at one side of the floating gate and in contact with the first dielectric layer. The drain region is disposed in the substrate at another side of the floating gate and separated from the first dielectric layer. The select gate is disposed on the substrate between the floating gate and the drain region. The third dielectric layer is disposed between the select gate and the substrate.

公开(公告)号：US20240136417A1

公开(公告)日：2024-04-25

申请号：US18395616

申请日：2023-12-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/41775 ,  H01L29/0607 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate is provided. A semiconductor channel layer is formed on the substrate. A semiconductor barrier layer is formed on the semiconductor channel layer. An etching process is performed to expose a portion of the semiconductor channel layer. A dielectric layer is formed to cover the semiconductor barrier layer and the exposed semiconductor channel layer. A first electrode is formed after forming the dielectric layer, where the first electrode includes a body portion and a vertical extension portion, the body portion is electrically connected to the semiconductor barrier layer, and a bottom surface of the vertical extension portion is lower than a top surface of the semiconductor channel layer.

公开(公告)号：US11968911B2

公开(公告)日：2024-04-23

申请号：US17518571

申请日：2021-11-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin ,  Yu-Ping Wang ,  Chien-Ting Lin

IPC: H10N52/01 ,  H10B61/00 ,  H10N52/00 ,  H10N52/80

CPC classification number: H10N52/01 ,  H10B61/00 ,  H10N52/00 ,  H10N52/80

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a first spin orbit torque (SOT) layer on the MTJ stack; forming a first hard mask on the first SOT layer; and using a second hard mask to pattern the first hard mask, the first SOT layer, and the MTJ stack to form a MTJ.