中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

151 records (took 0.028 seconds)

    METHOD OF WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY
    132.
    发明申请
    METHOD OF WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY 审中-公开
    写入旋转磁力随机存取存储器的方法

    公开(公告)号：US20160276012A1

    公开(公告)日：2016-09-22

    申请号：US15167758

    申请日：2016-05-27

    Applicant: Everspin Technologies, Inc.

    Inventor： Syed M. Alam ,  Thomas Andre ,  Matthew R. Croft ,  Chitra Subramanian ,  Halbert Lin

    IPC: G11C11/16

    CPC classification number: G11C11/1675 ,  G06F11/1048 ,  G06F11/1076 ,  G11C11/00 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0076 ,  G11C2029/0411

    Abstract: A spin-torque magnetoresistive memory includes array read circuits and array write circuits coupled to an array of magnetic bits. The array read circuits sample magnetic bits in the array, apply a write current pulse to the magnetic bits to set them to a first logic state, resample the magnetic bits using an additional offset current, and compare the results of sampling and resampling to determine the bit state for each magnetic bit. For each of the magnetic bits in the page having the second logic state, the array write circuits initiate a write-back, wherein the write-back includes applying a second write current pulse having opposite polarity in comparison with the first write current pulse to set the magnetic bit to the second state. A read or write operation may be received after initiation of the write-back where the write-back can be aborted for a portion of the bits in the case of a write operation. The write-back may be performed such that different portions of the magnetic bits are written back at different times, thereby staggering the write-back current pulses in time.

    Abstract translation: 自旋转矩磁阻存储器包括耦合到磁头阵列的阵列读取电路和阵列写入电路。 阵列读取电路对阵列中的磁头进行采样，向磁头施加写入电流脉冲以将其设置为第一逻辑状态，使用附加的偏移电流对磁性位进行重新采样，并比较采样和重采样的结果，以确定 每个磁头的位状态。 对于具有第二逻辑状态的页面中的每个磁性位，阵列写入电路启动回写，其中写回包括施加与第一写入电流脉冲相比具有相反极性的第二写入电流脉冲以设置 磁头到第二个状态。 在写回开始之后可以接收读取或写入操作，其中在写入操作的情况下可以中止一部分位的写回。 可以执行回写，使得磁头的不同部分在不同的时间被写回，从而及时地交错回写电流脉冲。

    MEMORY DEVICE WITH SHARED READ/WRITE CIRCUITRY
    133.
    发明申请
    MEMORY DEVICE WITH SHARED READ/WRITE CIRCUITRY 审中-公开
    具有共享读/写电路的存储器件

    公开(公告)号：US20160247551A1

    公开(公告)日：2016-08-25

    申请号：US15143820

    申请日：2016-05-02

    Applicant: Everspin Technologies, Inc.

    Inventor： Syed M. Alam ,  Chitra K. Subramanian

    IPC: G11C11/16

    CPC classification number: G11C11/1673 ,  G11C11/1659 ,  G11C11/1675

    Abstract: In some examples, a memory device may be configured to read or write multiple bit cells as part of the same operation. In some cases, the tunnel junctions forming the bit cells may be arranged to utilize shared read/write circuitry. For instance, the tunnel junctions may be arranged such that both tunnel junctions may be written using the same write voltages. In some cases, the bit cells may be configured such that each bit cell is driven to the same state, while in other cases, select bit cells may be driven high, while others are driven low.

    Abstract translation: 在一些示例中，存储器设备可以被配置为读取或写入多个位单元作为相同操作的一部分。 在一些情况下，形成比特单元的隧道结可以被布置成利用共享的读/写电路。 例如，隧道结可以被布置成使得两个隧道结可以使用相同的写入电压来写入。 在某些情况下，可以配置比特单元使得每个比特单元被驱动到相同的状态，而在其他情况下，选择比特单元可以被驱动为高，而其他的比特单元被驱动为低。

    Circuit and method for accessing a bit cell in a spin-torque MRAM
    136.
    发明授权
    Circuit and method for accessing a bit cell in a spin-torque MRAM 有权
    用于访问自旋扭矩MRAM中的位单元的电路和方法

    公开(公告)号：US09368181B2

    公开(公告)日：2016-06-14

    申请号：US14918998

    申请日：2015-10-21

    Applicant: Everspin Technologies, Inc.

    Inventor： Syed M. Alam ,  Thomas Andre

    IPC: G11C11/00 ,  G11C11/16

    CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/165 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1693

    Abstract: Circuitry and a method for regulating voltages applied to magnetoresistive bit cells of a spin-torque magnetoresistive random access memory (ST-MRAM) reduces time-dependent dielectric breakdown stress of the word line transistors. During a read or write operation, only the ends of the selected bit cells are pulled down to a low voltage and/or pulled up to a high voltage depending on the operation (write 0, write 1, and read) being performed. The ends of the unselected bit cells are held at a precharge voltage while separately timed signals pull up or pull down the ends of the selected bit cells during read and write operations.

    Abstract translation: 用于调节施加到自旋转矩磁阻随机存取存储器（ST-MRAM）的磁阻位元的电压的电路和方法降低了字线晶体管的时间依赖介电击穿应力。 在读或写操作期间，根据正在执行的操作（写0，写1和读），仅将所选位单元的端部下拉至低电压和/或上拉至高电压。 未选择的位单元的端部保持在预充电电压，而在读取和写入操作期间单独定时的信号上拉或下拉所选位单元的端部。

    Boosted supply voltage generator for a memory device and method therefore
    137.
    发明授权
    Boosted supply voltage generator for a memory device and method therefore 有权
    因此，用于存储器件的升压电源电压发生器和方法

    公开(公告)号：US09361964B1

    公开(公告)日：2016-06-07

    申请号：US15051794

    申请日：2016-02-24

    Applicant: Everspin Technologies, Inc.

    Inventor： Dietmar Gogl ,  Syed M. Alam ,  Thomas Andre ,  Halbert S. Lin

    IPC: G11C11/00 ,  G11C11/16

    CPC classification number: G11C11/1673 ,  G11C8/08 ,  G11C11/1657 ,  G11C11/1693 ,  G11C11/1697

    Abstract: A boosted supply voltage generator is selectively activated and deactivated to allow operations that are sensitive to variations on the boosted voltage to be performed with a stable boosted voltage. Techniques for deactivating and reactivating the voltage generator are also disclosed that enable more rapid recovery from deactivation such that subsequent operations can be commenced sooner. Such techniques include storing state information corresponding to the voltage generator when deactivated, where the stored state information is used when reactivating the voltage generator. Stored state information can include a state of a clock signal provided to the voltage generator.

    Abstract translation: 升压的电源电压发生器被选择性地激活和去激活，以允许以稳定的升压电压来执行对升压电压的变化敏感的操作。 还公开了用于停用和重新激活电压发生器的技术，其使得能够从停用中更快速地恢复，使得可以更快地开始后续操作。 这样的技术包括当停用时存储对应于电压发生器的状态信息，其中在重新激活电压发生器时使用存储的状态信息。 存储状态信息可以包括提供给电压发生器的时钟信号的状态。

    Memory device with shared read/write circuitry
    138.
    发明授权
    Memory device with shared read/write circuitry 有权
    具有共享读/写电路的存储器

    公开(公告)号：US09336849B2

    公开(公告)日：2016-05-10

    申请号：US14727981

    申请日：2015-06-02

    Applicant: Everspin Technologies, Inc.

    Inventor： Syed M. Alam ,  Chitra K. Subramanian

    IPC: G11C11/00 ,  G11C11/16

    CPC classification number: G11C11/1673 ,  G11C11/1659 ,  G11C11/1675

    Abstract: In some examples, a memory device may be configured to read or write multiple bit cells as part of the same operation. In some cases, the tunnel junctions forming the bit cells may be arranged to utilize shared read/write circuitry. For instance, the tunnel junctions may be arranged such that both tunnel junctions may be written using the same write voltages. In some cases, the bit cells may be configured such that each bit cell is driven to the same state, while in other cases, select bit cells may be driven high, while others are driven low.

    Abstract translation: 在一些示例中，存储器设备可以被配置为读取或写入多个位单元作为相同操作的一部分。 在一些情况下，形成比特单元的隧道结可以被布置成利用共享的读/写电路。 例如，隧道结可以被布置成使得两个隧道结可以使用相同的写入电压来写入。 在某些情况下，可以配置比特单元使得每个比特单元被驱动到相同的状态，而在其他情况下，选择比特单元可以被驱动为高，而其他的比特单元被驱动为低。

    Memory Device With Timing Overlap Mode
    139.
    发明申请
    Memory Device With Timing Overlap Mode 审中-公开
    具有定时重叠模式的存储器

    公开(公告)号：US20160104518A1

    公开(公告)日：2016-04-14

    申请号：US14973884

    申请日：2015-12-18

    Applicant: Everspin Technologies, Inc.

    Inventor： Thomas Andre ,  Syed M. Alam ,  Halbert S. Lin

    IPC: G11C7/12

    CPC classification number: G11C11/1675 ,  G06F12/0802 ,  G06F2212/222 ,  G11C7/00 ,  G11C7/1042 ,  G11C7/12 ,  G11C7/22 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/4076

    Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.

    Abstract translation: 在一些示例中，存储器设备被配置为接收预充电命令和激活命令。 响应于接收到所述预充电命令，响应于接收到所述激活命令，所述存储器装置执行与所述预充电命令相关的第一系列事件和与所述激活命令相关的第二系列事件。 存储器件延迟第二系列事件的开始直到第一系列事件完成。

    MEMORY DEVICE WITH SHARED READ/WRITE CIRCUITRY
    140.
    发明申请
    MEMORY DEVICE WITH SHARED READ/WRITE CIRCUITRY 有权

    公开(公告)号：US20160099038A1

    公开(公告)日：2016-04-07

    申请号：US14727981

    申请日：2015-06-02

    Applicant: Everspin Technologies, Inc.

    Inventor： Syed M. Alam ,  Chitra K. Subramanian

    IPC: G11C11/16

    CPC classification number: G11C11/1673 ,  G11C11/1659 ,  G11C11/1675

    Abstract: In some examples, a memory device may be configured to read or write multiple bit cells as part of the same operation. In some cases, the tunnel junctions forming the bit cells may be arranged to utilize shared read/write circuitry. For instance, the tunnel junctions may be arranged such that both tunnel junctions may be written using the same write voltages. In some cases, the bit cells may be configured such that each bit cell is driven to the same state, while in other cases, select bit cells may be driven high, while others are driven low.

Patent Agency Ranking