公开(公告)号：US08835262B2

公开(公告)日：2014-09-16

申请号：US13736294

申请日：2013-01-08

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0207 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: One method includes performing an etching process through a patterned mask layer to form trenches in a substrate that defines first and second fins, forming liner material adjacent the first fin to a first thickness, forming liner material adjacent the second fin to a second thickness different from the first thickness, forming insulating material in the trenches adjacent the liner materials and above the mask layer, performing a process operation to remove portions of the layer of insulating material and to expose portions of the liner materials, performing another etching process to remove portions of the liner materials and the mask layer to expose the first fin to a first height and the second fin to a second height different from the first height, performing another etching process to define a reduced-thickness layer of insulating material, and forming a gate structure around a portion of the first and second fin.

Abstract translation: 一种方法包括通过图案化的掩模层执行蚀刻工艺，以在限定第一和第二鳍片的衬底中形成沟槽，将邻近第一鳍片的衬垫材料形成第一厚度，将与第二鳍片相邻的衬垫材料形成为不同于第二厚度的第二厚度 所述第一厚度在所述沟槽中形成绝缘材料，所述沟槽邻近所述衬垫材料并且在所述掩模层上方，执行处理操作以去除所述绝缘材料层的部分并暴露所述衬垫材料的部分，执行另一蚀刻工艺以去除部分 所述衬垫材料和所述掩模层将所述第一翅片暴露于第一高度，并且所述第二鳍片具有不同于所述第一高度的第二高度，执行另一蚀刻工艺以限定绝缘材料的厚度减薄层，以及形成栅极结构 围绕第一和第二鳍的一部分。

公开(公告)号：US20140217482A1

公开(公告)日：2014-08-07

申请号：US13759209

申请日：2013-02-05

Applicant: GLOBALFOUNDRIES, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/40 ,  H01L29/49

CPC classification number: H01L21/28114 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method of fabricating an integrated circuit includes forming an interlayer dielectric (ILD) layer over a dummy gate stack. The dummy gate stack includes a dummy gate structure, a hardmask layer, and sidewall spacers formed over a semiconductor substrate. The method further includes removing at least an upper portion of the dummy gate stack to form a first opening within the ILD layer, extending the first opening to form a first extended opening by completely removing the dummy gate structure of the dummy gate stack, and depositing at least one workfunction material layer within the first opening and within the first extended opening. Still further, the method includes removing portions of the workfunction material within the first opening and depositing a low-resistance material over remaining portions of the workfunction material thereby forming a replacement metal gate structure that includes the remaining portion of the workfunction material and the low-resistance material.

Abstract translation: 制造集成电路的方法包括在虚拟栅极堆叠上形成层间电介质（ILD）层。 虚拟栅极堆叠包括伪栅极结构，硬掩模层和形成在半导体衬底上的侧壁间隔物。 该方法还包括去除伪栅极堆叠的至少上部以在ILD层内形成第一开口，通过完全去除虚拟栅极堆叠的伪栅极结构，延伸第一开口以形成第一扩展开口，并且沉积 在所述第一开口内和所述第一延伸开口内的至少一个功函数材料层。 此外，该方法包括去除第一开口内的功函件材料的一部分，并在工作功能材料的剩余部分上沉积低电阻材料，从而形成包括功函件材料和低功能材料的剩余部分的替换金属栅结构， 电阻材料。

公开(公告)号：US10916470B2

公开(公告)日：2021-02-09

申请号：US16290178

申请日：2019-03-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal K. Kamineni ,  Ruilong Xie ,  Kangguo Cheng ,  Adra V. Carr

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/532 ,  H01L21/8234 ,  H01L29/78

Abstract: Structures that include a field effect-transistor and methods of forming a structure that includes a field-effect transistor. A first field-effect transistor includes a first source/drain region, and a second field-effect transistor includes a second source/drain region. A first contact is arranged over the first source/drain region, and a second contact is arranged over the second source/drain region. A portion of a dielectric layer, which is composed of a low-k dielectric material, is laterally arranged between the first contact and the second contact.

公开(公告)号：US10790376B2

公开(公告)日：2020-09-29

申请号：US16105102

申请日：2018-08-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Chanro Park ,  Julien Frougier ,  Kangguo Cheng ,  Andre P. Labonte

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/45 ,  H01L21/768 ,  H01L27/088 ,  H01L21/027 ,  H01L21/311 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L21/3105 ,  H01L21/3213

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions and sidewall spacers; contacts connecting to at least one gate structure of the plurality of gate structures; and at least one metallization feature connecting to the source and drain regions and extending over the sidewall spacers.

公开(公告)号：US10770566B2

公开(公告)日：2020-09-08

申请号：US16594276

申请日：2019-10-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Julien Frougier ,  Ruilong Xie ,  Chanro Park ,  Kangguo Cheng

IPC: H01L29/66 ,  H01L21/764 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423

Abstract: A device is disclosed that includes an active layer, a gate structure positioned above a channel region of the active layer and a first sidewall spacer positioned adjacent the gate structure. The device also includes a gate cap layer positioned above the gate structure and an upper spacer that contacts sidewall surfaces of the gate cap layer, a portion of an upper surface of the gate structure and an inner surface of the first sidewall spacer.

公开(公告)号：US10770454B2

公开(公告)日：2020-09-08

申请号：US15948609

申请日：2018-04-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro Park ,  Ruilong Xie ,  Kangguo Cheng ,  Juntao Li

IPC: H01L27/108 ,  H01L27/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/762 ,  H01L49/02

Abstract: We report a semiconductor device, containing a semiconductor substrate; an isolation feature on the substrate; a plurality of gates on the isolation feature, wherein each gate comprises a gate electrode and a high-k dielectric layer disposed between the gate electrode and the isolation feature and disposed on and in contact with at least one side of the gate electrode; and a fill metal between the plurality of gates on the isolation feature. We also report methods of forming such a device, and a system for manufacturing such a device.

公开(公告)号：US10749038B2

公开(公告)日：2020-08-18

申请号：US16057579

申请日：2018-08-07

Applicant: International Business Machines Corporation ,  Globalfoundries Inc.

Inventor： Kangguo Cheng ,  Xin Miao ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: In one aspect, a method of forming a semiconductor device includes the steps of: forming an alternating series of sacrificial/active layers on a wafer and patterning it into at least one nano device stack; forming a dummy gate on the nano device stack; patterning at least one upper active layer in the nano device stack to remove all but a portion of the at least one upper active layer beneath the dummy gate; forming spacers on opposite sides of the dummy gate covering the at least one upper active layer that has been patterned; forming source and drain regions on opposite sides of the nano device stack, wherein the at least one upper active layer is separated from the source and drain regions by the spacers; and replacing the dummy gate with a replacement gate. A masking process is also provided to tailor the effective device width of select devices.

公开(公告)号：US20200027981A1

公开(公告)日：2020-01-23

申请号：US16038265

申请日：2018-07-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro PARK ,  Kangguo Cheng

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/768

Abstract: A fin cut last methodology for manufacturing a vertical FinFET includes forming a plurality of semiconductor fins over a substrate, forming shallow trench isolation between active fins and, following the formation of a functional gate of the active fins, using a selective etch to remove a sacrificial fin from within an isolation region. A further etching step can be used to remove a portion of the gate stack proximate to the sacrificial fin to create an isolation trench and a laterally-extending cavity within the isolation region that are back-filled with an isolation dielectric.

公开(公告)号：US20190312028A1

公开(公告)日：2019-10-10

申请号：US15948609

申请日：2018-04-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro Park ,  Ruilong Xie ,  Kangguo Cheng ,  Juntao Li

IPC: H01L27/06 ,  H01L29/78 ,  H01L49/02 ,  H01L21/762 ,  H01L21/8234

Abstract: We report a semiconductor device, containing a semiconductor substrate; an isolation feature on the substrate; a plurality of gates on the isolation feature, wherein each gate comprises a gate electrode and a high-k dielectric layer disposed between the gate electrode and the isolation feature and disposed on and in contact with at least one side of the gate electrode; and a fill metal between the plurality of gates on the isolation feature. We also report methods of forming such a device, and a system for manufacturing such a device.

公开(公告)号：US10439031B2

公开(公告)日：2019-10-08

申请号：US15338925

申请日：2016-10-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L23/525 ,  H01L27/112 ,  H01L29/417 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

Abstract: Structures for a vertical-transport field-effect transistor and an electrical fuse integrated into an integrated circuit, and methods of fabricating a vertical-transport field-effect transistor and an electrical fuse integrated into an integrated circuit. A doped semiconductor layer that includes a first region with a first electrode of the vertical electrical fuse and a second region with a first source/drain region of the vertical-transport field effect transistor. A semiconductor fin is formed on the first region of the doped semiconductor layer, and a fuse link is formed on the second region of the doped semiconductor layer. A second source/drain region is formed that is coupled with the fin. A gate structure is arranged vertically between the first source/drain region and the second source/drain region. A second electrode of the vertical fuse is formed such that the fuse link is arranged vertically between the first electrode and the second electrode.