公开(公告)号：US20150333136A1

公开(公告)日：2015-11-19

申请号：US14812150

申请日：2015-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Ajey Poovannummoottil Jacob ,  Andreas Knorr ,  Christopher Prindle

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45

CPC classification number: H01L29/41758 ,  H01L21/28518 ,  H01L21/31111 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/78

Abstract: One illustrative method disclosed herein includes removing the sidewall spacers and a gate cap layer so as to thereby expose an upper surface and sidewalls of a sacrificial gate structure, forming an etch stop layer above source/drain regions of a device and on the sidewalls and upper surface of the sacrificial gate structure, forming a first layer of insulating material above the etch stop layer, removing the sacrificial gate structure so as to define a replacement gate cavity that is laterally defined by portions of the etch stop layer, forming a replacement gate structure in the replacement gate cavity, and forming a second gate cap layer above the replacement gate structure.

Abstract translation: 本文公开的一种示例性方法包括去除侧壁间隔件和栅极盖层，从而暴露牺牲栅极结构的上表面和侧壁，在器件的源极/漏极区域上方以及在侧壁和上部上形成蚀刻停止层 牺牲栅极结构的表面，在蚀刻停止层上方形成第一绝缘材料层，去除牺牲栅极结构，以便限定由蚀刻停止层的部分横向限定的替代栅极腔，形成替代栅极结构 并且在替换栅极结构上方形成第二栅极盖层。

公开(公告)号：US09190411B2

公开(公告)日：2015-11-17

申请号：US13914808

申请日：2013-06-11

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation ,  Renesas Electronics Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Steven John Bentley ,  Murat Kerem Akarvardar ,  Jody Alan Fronheiser ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Toshiharu Nagumo

IPC: H01L21/84 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins.

Abstract translation: 本文的实施例提供了在互补金属氧化物鳍片场效应晶体管中的器件隔离。 具体地，半导体器件在衬底上形成有逆向掺杂层以最小化源极到漏极穿通泄漏。 一组高迁移率通道散热片形成在逆向掺杂层上，该组高迁移率通道散热片中的每一个包括高迁移率通道材料（例如硅或硅 - 锗）。 逆向掺杂层可以使用原位掺杂工艺或反掺杂剂逆向植入来形成。 该装置还可以包括位于逆向掺杂层和一组高迁移率通道翅片之间的碳衬垫，以防止载流子溢出到高迁移率通道翅片。

公开(公告)号：US09147730B2

公开(公告)日：2015-09-29

申请号：US14195344

申请日：2014-03-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andreas Knorr ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove

IPC: H01L21/84 ,  H01L29/06 ,  H01L21/306 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L21/3085 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes forming a plurality of initial fins in a substrate, wherein at least one of the initial fins is a to-be-removed fin, forming a material adjacent the initial fins, forming a fin removal masking layer above the plurality of initial fins, removing a desired portion of the at least one to-be-removed fin by: (a) performing a recess etching process on the material to remove a portion, but not all, of the material positioned adjacent the sidewalls of the at least one to-be-removed fin, (b) after performing the recess etching process, performing a fin recess etching process to remove a portion, but not all, of the at least one to be removed fin and (c) repeating steps (a) and (b) until the desired amount of the at least one to-be-removed fin is removed.

Abstract translation: 本文公开的一种说明性方法包括在基底中形成多个初始翅片，其中至少一个初始翅片是待去除翅片，形成与初始翅片相邻的材料，在多个 的初始翅片，通过以下步骤去除所述至少一个待去除的翅片的期望部分：（a）对所述材料执行凹陷蚀刻工艺以去除邻近所述第二侧壁的所述材料定位的部分（但不是全部） 至少一个待去除的翅片，（b）在执行凹陷蚀刻工艺之后，进行翅片凹槽蚀刻工艺以去除待除去的至少一个翅片的部分而不是全部，以及（c）重复步骤 （a）和（b），直到除去所需量的至少一个待去除的翅片。

公开(公告)号：US09147616B1

公开(公告)日：2015-09-29

申请号：US14471087

申请日：2014-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar

IPC: H01L21/84 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795

Abstract: One illustrative method disclosed herein includes, among other things, oxidizing a lower portion of an initial fin structure to thereby define an isolation region that vertically separates an upper portion of the initial fin structure from a semiconducting substrate, performing a recess etching process to remove a portion of the upper portion of the initial fin structure so as to define a recessed fin portion, forming a replacement fin on the recessed fin portion so as to define a final fin structure comprised of the replacement fin and the recessed fin portion, and forming a gate structure around at least a portion of the replacement fin.

Abstract translation: 本文公开的一种说明性方法包括氧化初始鳍结构的下部，从而限定将初始鳍结构的上部与半导体衬底垂直分离的隔离区，执行凹陷蚀刻工艺以去除 初始翅片结构的上部的一部分，以便限定一个凹入的翅片部分，在该凹入的翅片部分上形成一个替换翅片，以便限定由替换翅片和该凹入的翅片部分组成的最终翅片结构， 围绕替换翅片的至少一部分的门结构。

公开(公告)号：US20150255456A1

公开(公告)日：2015-09-10

申请号：US14195884

申请日：2014-03-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Min-hwa Chi

IPC: H01L27/088 ,  H01L29/161 ,  H01L21/266 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/02 ,  H01L29/16 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

Abstract: Embodiments herein provide approaches for forming a set of replacement fins in a semiconductor device. Specifically, a device is formed having a set of replacement fins over a substrate, each of the set of replacement fins comprising a first section separated from a second section by a liner layer, the first section having a lower dopant centration than a dopant concentration of the second section. In one embodiment, sequential epitaxial deposition with insitu doping is used to form the second section, the liner layer, and then the first section of each of the set of replacement fins. In another embodiment, the second section is formed over the substrate, and the liner layer is formed through a carbon implant. The first section is then epitaxially formed over the liner layer, and serves as the fin channel. As provided, upward dopant diffusion is suppressed, resulting in the first section of each fin being maintained with low doping so that the fin channel is fully depleted channel during device operation.

Abstract translation: 本文的实施例提供了在半导体器件中形成一组替换翅片的方法。 具体地说，在衬底上形成具有一组置换鳍片的器件，该组替换鳍片包括通过衬垫层与第二部分隔开的第一部分，第一部分具有比掺杂剂浓度低的掺杂剂浓度 第二部分。 在一个实施例中，使用具有内置掺杂的顺序外延沉积来形成第二部分，衬垫层，然后形成该组替换散热片中的每一个的第一部分。 在另一个实施例中，第二部分形成在衬底上，并且衬里层通过碳植入物形成。 然后第一部分外延地形成在衬里层上，并且用作鳍状通道。 如上所述，向上掺杂剂扩散被抑制，导致每个鳍片的第一部分被保持低掺杂，使得鳍片沟道在器件操作期间是完全耗尽的沟道。

公开(公告)号：US20150249127A1

公开(公告)日：2015-09-03

申请号：US14195344

申请日：2014-03-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andreas Knorr ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove

IPC: H01L29/06 ,  H01L21/311 ,  H01L21/308 ,  H01L21/306

CPC classification number: H01L21/3085 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes forming a plurality of initial fins in a substrate, wherein at least one of the initial fins is a to-be-removed fin, forming a material adjacent the initial fins, forming a fin removal masking layer above the plurality of initial fins, removing a desired portion of the at least one to-be-removed fin by: (a) performing a recess etching process on the material to remove a portion, but not all, of the material positioned adjacent the sidewalls of the at least one to-be-removed fin, (b) after performing the recess etching process, performing a fin recess etching process to remove a portion, but not all, of the at least one to be removed fin and (c) repeating steps (a) and (b) until the desired amount of the at least one to-be-removed fin is removed.

Abstract translation: 本文公开的一种说明性方法包括在基底中形成多个初始翅片，其中至少一个初始翅片是待去除翅片，形成与初始翅片相邻的材料，在多个 的初始翅片，通过以下步骤去除所述至少一个待去除的翅片的期望部分：（a）对所述材料执行凹陷蚀刻工艺以去除邻近所述第二侧壁的所述材料定位的部分（但不是全部） 至少一个待去除的翅片，（b）在执行凹陷蚀刻工艺之后，进行翅片凹槽蚀刻工艺以去除待除去的至少一个翅片的部分而不是全部，以及（c）重复步骤 （a）和（b），直到除去所需量的至少一个待去除的翅片。

公开(公告)号：US09123627B1

公开(公告)日：2015-09-01

申请号：US14267010

申请日：2014-05-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Ajey Poovannummoottil Jacob ,  Shurong Liang

IPC: H01L29/165 ,  H01L29/66 ,  H01L29/36 ,  H01L21/306 ,  H01L21/322

CPC classification number: H01L29/165 ,  H01L21/30608 ,  H01L21/3221 ,  H01L21/76224 ,  H01L29/1054 ,  H01L29/36 ,  H01L29/66795 ,  H01L29/785

Abstract: One method disclosed herein includes removing at least a portion of a fin to thereby define a fin trench in a layer of insulating material, forming first and second layers of semiconductor material in the fin trench, after forming the second layer of semiconductor material, performing an anneal process to induce defect formation in at least the first layer of semiconductor material, wherein, after the anneal process is performed, the upper surface of the second layer of semiconductor material is substantially defect-free, forming a layer of channel semiconductor material on the upper surface of the second layer of semiconductor material and forming a gate structure around at least a portion of the channel semiconductor material.

Abstract translation: 本文公开的一种方法包括去除鳍片的至少一部分，从而在绝缘材料层中限定翅片沟槽，在形成第二层半导体材料之后，在翅片沟槽中形成半导体材料的第一和第二层， 退火工艺以在至少第一半导体材料层中引起缺陷形成，其中，在进行退火处理之后，第二半导体材料层的上表面基本上是无缺陷的，在第二层上形成沟道半导体材料层 第二层半导体材料的上表面，并围绕沟道半导体材料的至少一部分形成栅极结构。

公开(公告)号：US09076842B2

公开(公告)日：2015-07-07

申请号：US14011125

申请日：2013-08-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Steven John Bentley ,  Bartlomiej Jan Pawlak

IPC: H01L21/302 ,  H01L21/764 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L21/764 ,  H01L21/02488 ,  H01L21/02587 ,  H01L21/762 ,  H01L29/66795 ,  H01L29/785

Abstract: A first semiconductor structure includes a bulk silicon substrate and one or more original silicon fins coupled to the bulk silicon substrate. A dielectric material is conformally blanketed over the first semiconductor structure and recessed to create a dielectric layer. A first cladding material is deposited adjacent to the original silicon fin, after which the original silicon fin is removed to form a second semiconductor structure having two fins that are electrically isolated from the bulk silicon substrate. A second cladding material is patterned adjacent to the first cladding material to form a third semiconductor structure having four fins that are electrically isolated from the bulk silicon substrate.

Abstract translation: 第一半导体结构包括体硅衬底和耦合到体硅衬底的一个或多个原始硅鳍片。 电介质材料保形地覆盖在第一半导体结构上并凹进以产生电介质层。 第一覆层材料沉积在原始硅鳍片附近，之后去除原始硅片以形成具有与体硅衬底电隔离的两个散热片的第二半导体结构。 第二包层材料被图案化为与第一包层材料相邻以形成具有与体硅衬底电隔离的四个散热片的第三半导体结构。

公开(公告)号：US20150140761A1

公开(公告)日：2015-05-21

申请号：US14599873

申请日：2015-01-19

Applicant: GLOBALFOUNDRIES INC. ,  International Business Machines Corporation ,  Renesas Electronics Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Steven Bentley ,  Toshiharu Nagumo ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz

IPC: H01L21/8238 ,  H01L21/762 ,  H01L21/266 ,  H01L21/02

CPC classification number: H01L21/823821 ,  H01L21/02227 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/266 ,  H01L21/3086 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0646 ,  H01L29/66795 ,  H01L29/7851

Abstract: Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of replacement fins is formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material (e.g., silicon, or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of replacement fins to prevent carrier spill-out to the replacement fins.

Abstract translation: 本文的实施例提供了在互补金属氧化物鳍片场效应晶体管中的器件隔离的方法。 具体地，半导体器件在衬底上形成有逆向掺杂层以最小化源极到漏极穿通泄漏。 在逆向掺杂层上形成一组替代翅片，该组替换鳍片中的每一个包括高迁移率通道材料（例如，硅或硅 - 锗）。 逆向掺杂层可以使用原位掺杂工艺或反掺杂剂逆向植入来形成。 该装置还可以包括位于逆向掺杂层和该替代翅片组之间的碳衬垫，以防止载体溢出到置换翅片。

公开(公告)号：US09006077B2

公开(公告)日：2015-04-14

申请号：US13971937

申请日：2013-08-21

Applicant: GlobalFoundries, Inc.

Inventor： Murat Kerem Akarvardar ,  Ajey Poovannummoottil Jacob

IPC: H01L21/76 ,  H01L21/84 ,  H01L21/00 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76264 ,  H01L21/02488 ,  H01L21/76224 ,  H01L29/66795

Abstract: Methods for fabricating integrated circuits and FinFET transistors on bulk substrates with active channel regions isolated from the substrate with an insulator are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit includes forming fin structures overlying a semiconductor substrate, wherein each fin structure includes a channel material and extends in a longitudinal direction from a first end to a second end. The method deposits an anchoring material over the fin structures. The method includes recessing the anchoring material to form trenches adjacent the fin structures, wherein the anchoring material remains in contact with the first end and the second end of each fin structure. Further, the method forms a void between the semiconductor substrate and the channel material of each fin structure with a gate length independent etching process, wherein the channel material of each fin structure is suspended over the semiconductor substrate.

Abstract translation: 提供了在具有与绝缘体与衬底隔离的有源沟道区的本体衬底上制造集成电路和FinFET晶体管的方法。 根据示例性实施例，一种用于制造集成电路的方法包括形成覆盖半导体衬底的鳍状结构，其中每个鳍结构包括沟道材料并且在纵向方向上从第一端延伸到第二端。 该方法将锚固材料沉积在翅片结构上。 该方法包括使锚固材料凹入以形成邻近翅片结构的沟槽，其中锚定材料保持与每个翅片结构的第一端和第二端接触。 此外，该方法在半导体衬底和每个鳍结构的沟道材料之间形成空隙，栅极长度独立蚀刻工艺，其中每个鳍结构的沟道材料悬置在半导体衬底上。