公开(公告)号：US10832960B2

公开(公告)日：2020-11-10

申请号：US16270149

申请日：2019-02-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jingyun Zhang ,  Takashi Ando ,  Choonghyun Lee

IPC: H01L21/82 ,  H01L21/32 ,  H01L21/8234 ,  H01L21/324 ,  H01L29/423 ,  H01L27/088

Abstract: A method is presented for attaining different gate dielectric thicknesses across a plurality of field effect transistor (FET) devices. The method includes forming an interfacial dielectric around alternate semiconductor layers of the plurality of FET devices, depositing a first sacrificial capping layer over the plurality of FET devices, selectively removing the first sacrificial capping layer from a first set of the plurality of FET devices, depositing a second sacrificial capping layer and an oxygen blocking layer, selectively removing the oxygen blocking layer from a second set of the plurality of FET devices, and performing an anneal to create the different gate dielectric thicknesses for each of the plurality of FET devices.

公开(公告)号：US10818753B2

公开(公告)日：2020-10-27

申请号：US16356552

申请日：2019-03-18

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Alexander Reznicek ,  Injo Ok ,  Soon-Cheon Seo

IPC: H01L29/10 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/02 ,  H01L29/16 ,  H01L29/66

Abstract: A vertical transport field effect transistor (VTFET) is provided that includes a vertical semiconductor channel material structure (i.e., fin or pillar) having a V-shaped groove located in the topmost surface thereof. A top source/drain structure is formed in contact with the V-shaped groove present in the topmost surface of the vertical semiconductor channel material structure. No drive-in anneal is needed to form the top source/drain structure. The presence of the V-shaped groove at the top junction region provides a VTFET that has improved device performance.

公开(公告)号：US10804165B2

公开(公告)日：2020-10-13

申请号：US16440095

申请日：2019-06-13

Applicant: International Business Machines Corporation

Inventor： Soon-Cheon Seo ,  Choonghyun Lee ,  Injo Ok

IPC: H01L21/70 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L27/092 ,  H01L29/786 ,  H01L29/423 ,  H01L29/775 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: Techniques for source/drain isolation in nanosheet devices are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of sacrificial/active channel nanosheets as a stack on a substrate; forming gates on the stack; forming spacers alongside opposite sidewalls of the gates; patterning the stack, in between the spacers, into individual PFET/NFET stacks and pockets in the substrate; laterally recessing the sacrificial nanosheets in the PFET/NFET stacks to expose tips of the active channel nanosheets in the PFET/NFET stacks; forming inner spacers alongside the PFET/NFET stacks covering the tips of the active channel nanosheets; forming a protective layer lining the pockets; and selectively etching back the inner spacers to expose tips of the active channel nanosheets and epitaxially growing source and drains from the exposed tips of the active channel nanosheets sequentially in the PFET/NFET stacks. A nanosheet device is also provided.

公开(公告)号：US20200295256A1

公开(公告)日：2020-09-17

申请号：US16355148

申请日：2019-03-15

Applicant: International Business Machines Corporation

Inventor： Pouya Hashemi ,  Takashi Ando ,  Dimitri Houssameddine ,  Alexander Reznicek ,  Jingyun Zhang ,  Choonghyun Lee

IPC: H01L43/12 ,  H01L27/22

Abstract: A replacement bottom electrode structure process is provided in which a patterned stack containing a MTJ pillar and a top electrode structure is fabricated and passivated on a sacrificial dielectric material plug that is embedded in a dielectric capping layer. The sacrificial dielectric material plug is then removed and replaced with a bottom electrode structure. The replacement bottom electrode structure process of the present application allows the MTJ patterning to be misalignment tolerate and fully eliminates the potential yield loss from the bottom electrode structure.

公开(公告)号：US10756170B2

公开(公告)日：2020-08-25

申请号：US15954663

申请日：2018-04-17

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Juntao Li ,  Choonghyun Lee ,  Shogo Mochizuki

IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02

Abstract: Vertical field effect transistor (VFET) structures and methods of fabrication with improved junction sharpness and reduced parasitic capacitance between the top source or drain and the surrounding metal gate includes a non-uniform top spacer in the top source or drain formed by an oxidation process. The top spacer has a thickness that is thinner at an interface between the top source or drain region and the vertically oriented channel region of the fin structure relative to the thickness of the top spacer layer away from the interface.

公开(公告)号：US10749012B2

公开(公告)日：2020-08-18

申请号：US16454587

申请日：2019-06-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Choonghyun Lee ,  Shogo Mochizuki

IPC: H01L21/02 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/78

Abstract: A method of fabricating a semiconductor device includes forming a fin on a substrate. Source/drain regions are arranged on the substrate on opposing sides of the fin. The method includes depositing a semiconductor layer on the source/drain regions. The method includes depositing a germanium containing layer on the fin and the semiconductor layer. The method further includes applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer.

公开(公告)号：US10748994B2

公开(公告)日：2020-08-18

申请号：US16564823

申请日：2019-09-09

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Takashi Ando ,  Jingyun Zhang ,  Choonghyun Lee ,  Pouya Hashemi

IPC: H01L29/06 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/423 ,  H01L29/08 ,  H01L29/49 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66 ,  H01L21/28 ,  H01L21/285 ,  H01L27/12 ,  H01L29/786 ,  H01L21/84 ,  H01L27/092 ,  H01L27/06 ,  H01L29/775 ,  H01L21/822

Abstract: A semiconductor structure is provided that includes a pFET device including a first functional gate structure containing at least a p-type work function metal and present on physically exposed surfaces, and between, each Si channel material nanosheet of a first set of vertically stacked and suspended Si channel material nanosheets. The structure further includes an nFET device stacked vertically above the pFET device. The nFET device includes a second functional gate structure containing at least an n-type work function metal present on physically exposed surfaces, and between, each Si channel material nanosheet of a second set of vertically stacked and suspended Si channel material nanosheets.

公开(公告)号：US20200258785A1

公开(公告)日：2020-08-13

申请号：US16270149

申请日：2019-02-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jingyun Zhang ,  Takashi Ando ,  Choonghyun Lee

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L21/324

Abstract: A method is presented for attaining different gate dielectric thicknesses across a plurality of field effect transistor (FET) devices. The method includes forming an interfacial dielectric around alternate semiconductor layers of the plurality of FET devices, depositing a first sacrificial capping layer over the plurality of FET devices, selectively removing the first sacrificial capping layer from a first set of the plurality of FET devices, depositing a second sacrificial capping layer and an oxygen blocking layer, selectively removing the oxygen blocking layer from a second set of the plurality of FET devices, and performing an anneal to create the different gate dielectric thicknesses for each of the plurality of FET devices.

公开(公告)号：US20200235209A1

公开(公告)日：2020-07-23

申请号：US16255430

申请日：2019-01-23

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Choonghyun Lee ,  Takashi Ando ,  Jingyun Zhang ,  Pouya Hashemi

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/167 ,  H01L29/165 ,  H01L21/02

Abstract: A FinFET having an asymmetric threshold voltage distribution is provided by modifying a portion of the channel region of a semiconductor fin that is nearest to the drain side with an epitaxial semiconductor material layer. In some embodiments, the channel region of the semiconductor fin nearest to the drain side is trimmed prior to forming the epitaxial semiconductor material layer.

公开(公告)号：US10720502B2

公开(公告)日：2020-07-21

申请号：US16166384

申请日：2018-10-22

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Pouya Hashemi ,  Choonghyun Lee ,  Alexander Reznicek ,  Jingyun Zhang

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a fin having a fin bottom region. A charged region is formed on a sidewall of the fin bottom region, wherein the charged region includes charged particles, and wherein the fin bottom region is formed from an undoped semiconductor material. The charged particles attract charge carriers in the fin bottom region toward and adjacent to the sidewall of the fin bottom region, wherein the charge carriers form a current path through the undoped semiconductor material of the fin bottom region.