公开(公告)号：US11335730B2

公开(公告)日：2022-05-17

申请号：US16702103

申请日：2019-12-03

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Praneet Adusumilli ,  Reinaldo Vega ,  Cheng Chi

IPC: H01L27/24 ,  H01L45/00

Abstract: A vertical resistive switching memory device is provided that includes a resistive random access memory (ReRAM) stack embedded in a material stack of alternating layers of an interlayer dielectric material and a recessed electrode material. A selector device encapsulates a portion of the ReRAM stack and is present in an undercut region that is laterally adjacent to each of the recessed electrode material layers of the material stack.

公开(公告)号：US20220006009A1

公开(公告)日：2022-01-06

申请号：US17480248

申请日：2021-09-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Praneet Adusumilli ,  Jianshi Tang ,  Reinaldo Vega

IPC: H01L45/00 ,  H01L27/24

Abstract: A method is presented for enabling heat dissipation in resistive random access memory (RRAM) devices. The method includes forming a first thermal conducting layer over a bottom electrode, depositing a metal oxide liner over the first thermal conducting layer, forming a second thermal conducting layer over the metal oxide liner, recessing the second thermal conducting layer to expose the first thermal conducting layer, and forming a top electrode in direct contact with the first and second thermal conducting layers.

公开(公告)号：US11211452B1

公开(公告)日：2021-12-28

申请号：US16916736

申请日：2020-06-30

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Reinaldo Vega ,  Kangguo Cheng ,  Chanro Park ,  Juntao Li

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/786 ,  H01L29/161 ,  H01L29/06 ,  H01L29/45 ,  H01L29/08 ,  H01L21/8234

Abstract: Embodiments of the invention are directed to a method of performing fabrication operations to form a transistor, wherein the fabrication operations include forming a source or drain (S/D) region having stacked, spaced-apart, and doped S/D layers. The fabrication operations further include forming a multi-region S/D contact structure configured to contact a top surface, a bottom surface, and sidewalls of each of the stacked, spaced-apart, and doped S/D layers.

公开(公告)号：US20210167128A1

公开(公告)日：2021-06-03

申请号：US16702103

申请日：2019-12-03

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Praneet Adusumilli ,  Reinaldo Vega ,  Cheng Chi

IPC: H01L27/24 ,  H01L45/00

Abstract: A vertical resistive switching memory device is provided that includes a resistive random access memory (ReRAM) stack embedded in a material stack of alternating layers of an interlayer dielectric material and a recessed electrode material. A selector device encapsulates a portion of the ReRAM stack and is present in an undercut region that is laterally adjacent to each of the recessed electrode material layers of the material stack.

公开(公告)号：US20210119122A1

公开(公告)日：2021-04-22

申请号：US16655038

申请日：2019-10-16

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Jianshi Tang ,  Praneet Adusumilli ,  Reinaldo Vega

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: Resistive memory with core and shell oxides and interface dipoles for controlled filament formation is provided. In one aspect, a ReRAM device includes at least one ReRAM cell having a substrate; a bottom electrode disposed on the substrate; spacers formed from a low group electron negativity material disposed on the bottom electrode; a core formed from a high group electron negativity material present between the spacers; and a top electrode over and in contact with the spacers and the core, wherein a combination of the low group electron negativity material for the spacers and the high group electron negativity material for the core generates an interface dipole pointing toward the core. Methods of forming and operating a ReRAM device are also provided.

公开(公告)号：US10892181B2

公开(公告)日：2021-01-12

申请号：US16807716

申请日：2020-03-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Huimei Zhou ,  Gen Tsutsui ,  Veeraraghavan S. Basker ,  Andrew M. Greene ,  Dechao Guo ,  Huiming Bu ,  Reinaldo Vega

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66 ,  H01L29/78 ,  H01L21/32

Abstract: Integrated chips include a semiconductor fin that has a first active region and a second active region that are electrically separated by an oxide region that completely penetrates the semiconductor fin. A first semiconductor device is formed on the first active region. A second semiconductor device formed on the second active region.

公开(公告)号：US20210005813A1

公开(公告)日：2021-01-07

申请号：US16458857

申请日：2019-07-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jianshi Tang ,  Takashi Ando ,  Reinaldo Vega ,  Praneet Adusumilli

IPC: H01L45/00 ,  H01L27/24

Abstract: Devices with settable resistance and methods of forming the same include forming vertical dielectric structures from heterogeneous dielectric materials on a first electrode. A second electrode is formed on the vertical dielectric structures.

公开(公告)号：US10811413B2

公开(公告)日：2020-10-20

申请号：US16101659

申请日：2018-08-13

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Reinaldo Vega ,  Choonghyun Lee ,  Hari Mallela ,  Li-Wen Hung

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

Abstract: Multi-voltage threshold vertical transport transistors and methods of fabrication generally include forming the transistors with vertically oriented silicon fin channels for both the n-type doped field effect transistors (nFET) and the p-type doped field effect transistors (pFET). A silicon oxynitride interfacial layer is provided on sidewalls of the fins in the nFET and a silicon dioxide interfacial with aluminum is provided on sidewalls of the fins in the pFET to provide an aluminum induced dipole. A high k dielectric overlays the interfacial layers and a common work function metal overlays the high k dielectric layer to define a gate structure.

公开(公告)号：US20200327941A1

公开(公告)日：2020-10-15

申请号：US16379250

申请日：2019-04-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jianshi Tang ,  Praneet Adusumilli ,  Reinaldo Vega ,  Takashi Ando

IPC: G11C13/02 ,  G11C13/00 ,  G11C11/56

Abstract: A method is presented for mitigating conductance drift in intercalation cells for neuromorphic computing. The method includes forming a first electro-chemical random access memory (ECRAM) structure over a substrate and forming a second ECRAM over the substrate, the first and second ECRAMs sharing a common contact. The common contact can be either a source contact or a drain contact. Each of the first and second ECRAMs can include a tungsten oxide layer, an electrolyte layer, and a gate contact.

公开(公告)号：US20180342525A1

公开(公告)日：2018-11-29

申请号：US16010589

申请日：2018-06-18

Applicant: International Business Machines Corporation

Inventor： Michael A. Guillorn ,  Robert R. Robison ,  Reinaldo Vega ,  Rajasekhar Venigalla

IPC: H01L27/11 ,  H01L21/84

CPC classification number: H01L27/1108 ,  H01L21/8221 ,  H01L21/84 ,  H01L21/845 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/78618 ,  H01L29/78696

Abstract: A structure comprises a first channel region forming an n-channel device; a second channel region forming a p-channel device, the p-channel device being stacked with the n-channel device in a vertical orientation; a gate positioned around the stacked n-channel device and p-channel device; and at least one source region and at least one drain region extending from each of the n-channel device and the p-channel device. Each of the at least one source region and the at least one drain region within the stacked n-channel device and p-channel device are independently contacted.