公开(公告)号：US08890121B1

公开(公告)日：2014-11-18

申请号：US13887804

申请日：2013-05-06

Applicant: International Business Machines Corporation

Inventor： Shu-Jen Han ,  Ajay K. Royyuru ,  Gustavo A. Stolovitzky ,  Deqiang Wang

IPC: H01L29/06

CPC classification number: C12Q1/6869 ,  G01N27/4145 ,  G01N27/4146 ,  G01N33/48721 ,  Y10S977/924 ,  C12Q2563/116 ,  C12Q2563/157 ,  C12Q2565/631

Abstract: A technique is provided for base recognition in an integrated device is provided. A target molecule is driven into a nanopore of the integrated device. The integrated device includes a nanowire separated into a left nanowire part and a right nanowire part to form a nanogap in between, a source pad connected to the right nanowire part, a drain pad connected to the left nanowire part, and the nanopore. The source pad, the drain pad, the right nanowire part, the left nanowire part, and the nanogap together form a transistor. The nanogap is part of the nanopore. A transistor current is measured while a single base of the target molecule is in the nanogap of the nanopore, and the single base affects the transistor current. An identity of the single base is determined according to a change in the transistor current.

Abstract translation: 提供了一种用于集成设备中的基础识别的技术。 靶分子被驱动到集成器件的纳米孔中。 集成器件包括分离成左纳米线部分的纳米线和右纳米线部分，以在其间形成纳米间隙，连接到右纳米线部分的源极焊盘，连接到左纳米线部分的漏极焊盘和纳米孔。 源极焊盘，漏极焊盘，右侧的纳米线部分，左侧的纳米线部分和纳米光栅一起形成晶体管。 纳米孔是纳米孔的一部分。 测量晶体管电流，同时目标分子的单个碱基位于纳米孔的纳米隙中，单个碱基影响晶体管电流。 根据晶体管电流的变化确定单个基极的身份。

公开(公告)号：US20140332851A1

公开(公告)日：2014-11-13

申请号：US14027609

申请日：2013-09-16

Applicant: International Business Machines Corporation

Inventor： Cheng-Wei Cheng ,  Shu-Jen Han ,  Masaharu Kobayashi ,  Ko-Tao Lee ,  Devendra K. Sadana ,  Kuen-Ting Shiu

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, a method of forming a semiconductor device is provided that may include forming a semiconductor device including a gate structure on a channel portion of III-V semiconductor substrate. The III-V semiconductor substrate including a III-V base substrate layer, an aluminum containing III-V semiconductor layer that is present on the III-V base substrate layer, and a III-V channel layer. Oxidizing a portion of the aluminum containing III-V semiconductor layer on opposing sides of the gate structure. Forming a raised source region and a raised drain region over the portion of the aluminum containing III-V semiconductor layer that has been oxidized. Forming interconnects to the raised source region and the raised drain region.

公开(公告)号：US20140312413A1

公开(公告)日：2014-10-23

申请号：US13969013

申请日：2013-08-16

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Shu-Jen Han ,  Yu Lu ,  Keith Kwong Hon Wong

IPC: H01L29/417 ,  H01L29/78

CPC classification number: H01L29/66045 ,  H01L21/02527 ,  H01L21/043 ,  H01L21/044 ,  H01L21/30604 ,  H01L29/1606 ,  H01L29/41733 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/78684 ,  H01L51/0048 ,  H01L51/0545

Abstract: Transistors with self-aligned source/drain regions a gate structure embedded in a substrate; self-aligned source and drain contacts embedded in the substrate around the gate structure; and a channel layer over the gate structure and self-aligned source and drain contacts. The source and drain contacts extend above the channel layer.

Abstract translation: 具有自对准源极/漏极区域的晶体管，嵌入基板中的栅极结构; 嵌入在栅极结构周围的衬底中的自对准源极和漏极接触; 以及栅极结构和自对准源极和漏极触点之间的沟道层。 源极和漏极触点在沟道层上方延伸。

公开(公告)号：US20140158551A1

公开(公告)日：2014-06-12

申请号：US13706784

申请日：2012-12-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ali Afzali-Ardakani ,  Shu-Jen Han

IPC: G01N27/414 ,  H01L51/00

CPC classification number: G01N27/4146 ,  B82Y10/00 ,  B82Y15/00 ,  B82Y40/00 ,  G01N33/5438 ,  G01N33/551 ,  H01L51/0045 ,  H01L51/0048 ,  H01L51/0067 ,  H01L51/0072 ,  H01L51/0558

Abstract: Sensors, processes for manufacturing the sensors, and processes of detecting a target molecule with the sensor generally includes a substrate including a channel and first and second electrodes electrically connected to the channel, wherein the channel includes a monolayer of surface functionalized graphene or surface functionalized carbon nanotubes, wherein the surface functionalized graphene or surface functionalized carbon nanotubes include an imidazolidone compound.

Abstract translation: 用于制造传感器的传感器，制造传感器的过程以及用传感器检测目标分子的过程通常包括包括通道的基板和电连接到通道的第一和第二电极，其中通道包括单层的表面官能化石墨烯或表面官能化碳 纳米管，其中所述表面官能化石墨烯或表面官能化碳纳米管包括咪唑烷酮化合物。

公开(公告)号：US08735947B1

公开(公告)日：2014-05-27

申请号：US13693285

申请日：2012-12-04

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Shu-Jen Han ,  Fei Liu ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC: G01C19/00

CPC classification number: H01L29/66666 ,  B82Y10/00 ,  B82Y40/00 ,  H01H1/0094 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/938

Abstract: Non-volatile switches and methods for making the same include a gate material formed in a recess of a substrate; a flexible conductive element disposed above the gate material, separated from the gate material by a gap, where the flexible conductive element is supported on at least two points across the gap, and where a voltage above a gate threshold voltage causes a deformation in the flexible conductive element such that the flexible conductive element comes into contact with a drain in the substrate, thereby closing a circuit between the drain and a source terminal. The gap separating the flexible conductive element and the gate material is sized to create a negative threshold voltage at the gate material for opening the circuit.

Abstract translation: 非易失性开关及其制造方法包括形成在基板的凹部中的栅极材料; 设置在栅极材料上方的柔性导电元件，通过间隙与栅极材料分离，其中柔性导电元件被支撑在穿过间隙的至少两个点上，并且其中栅极阈值电压以上的电压导致柔性导体元件的变形 导电元件，使得柔性导电元件与衬底中的漏极接触，从而封闭漏极和源极端子之间的电路。 分离柔性导电元件和栅极材料的间隙的尺寸设计成在栅极材料处产生用于打开电路的负阈值电压。

公开(公告)号：US20130171813A1

公开(公告)日：2013-07-04

申请号：US13775369

申请日：2013-02-25

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Yanfeng Wang

IPC: H01L29/66

CPC classification number: H01L29/42368 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L29/66477

Abstract: A method for forming a field effect transistor (FET) device includes forming a dielectric layer on a substrate, forming a first metal layer on the dielectric layer, removing a portion of the first metal layer to expose a portion of the dielectric layer, forming a second metal layer on the dielectric layer and the first metal layer, and removing a portion of the first metal layer and the second metal layer to define a boundary region between a first FET device and a second FET device.

Abstract translation: 一种用于形成场效应晶体管（FET）器件的方法，包括在衬底上形成电介质层，在电介质层上形成第一金属层，去除第一金属层的一部分以露出电介质层的一部分，形成 在所述电介质层和所述第一金属层上的第二金属层，以及去除所述第一金属层和所述第二金属层的一部分，以限定第一FET器件和第二FET器件之间的边界区域。

公开(公告)号：US11150184B2

公开(公告)日：2021-10-19

申请号：US16653715

申请日：2019-10-15

Applicant: International Business Machines Corporation

Inventor： Abram L. Falk ,  Damon B. Farmer ,  Shu-Jen Han

IPC: G01N21/552 ,  G01N21/3504

Abstract: Differential, plasmonic, non-dispersive infrared gas sensors are provided. In one aspect, a gas sensor includes: a plasmonic resonance detector including a differential plasmon resonator array that is resonant at different wavelengths of light; and a light source incident on the plasmonic resonance detector. The differential plasmon resonator array can include: at least one first set of plasmonic resonators interwoven with at least one second set of plasmonic resonators, wherein the at least one first set of plasmonic resonators is configured to be resonant with light at a first wavelength, and wherein the at least one second set of plasmonic resonators is configured to be resonant with light at a second wavelength. A method for analyzing a target gas and a method for forming a plasmonic resonance detector are also provided.

公开(公告)号：US10714649B2

公开(公告)日：2020-07-14

申请号：US16590912

申请日：2019-10-02

Applicant: International Business Machines Corporation

Inventor： Damon Farmer ,  Shu-Jen Han

IPC: H01L31/101 ,  H01L31/0224 ,  H01L31/18 ,  H01L31/0296 ,  H01L31/0352

Abstract: A method of fabricating a visibly transparent, ultraviolet (UV) photodetector is provided. The method includes laying a first electrode onto a substrate surface, the first electrode being formed of a carbon-based, single-layer material. A block is patterned over an end of the first electrode and portions of the substrate surface. The block is formed of a visibly transparent material that is able to be deposited into the block at 75° C.-125° C. In addition, the method includes masking a section of the block and exposed sections of the first electrode. A second electrode is laid onto an unmasked section of the block with an end of the second electrode laid onto the substrate surface. The second electrode is formed of the carbon-based, single-layer material.

公开(公告)号：US10672986B2

公开(公告)日：2020-06-02

申请号：US15952570

申请日：2018-04-13

Applicant: International Business Machines Corporation

Inventor： Shu-Jen Han

IPC: H01L51/00 ,  C01B32/168 ,  B82Y40/00 ,  B82Y30/00

Abstract: Sub-lithographic structures configured for selective placement of carbon nanotubes and methods of fabricating the same generally includes alternating conformal first and second layers provided on a topographical pattern formed in a dielectric layer. The conformal layers can be deposited by atomic layer deposition or chemical vapor deposition at thicknesses less than 5 nanometers. A planarized surface of the alternating conformal first and second layers provides an alternating pattern of exposed surfaces corresponding to the first and second layer, wherein a width of at least a portion of the exposed surfaces is substantially equal to the thickness of the corresponding first and second layers. The first layer is configured to provide an affinity for carbon nanotubes and the second layer does not have an affinity such that the carbon nanotubes can be selectively placed onto the exposed surfaces of the alternating pattern corresponding to the first layer.

公开(公告)号：US10665799B2

公开(公告)日：2020-05-26

申请号：US15210491

申请日：2016-07-14

Applicant: International Business Machines Corporation

Inventor： Damon B. Farmer ,  Shu-Jen Han ,  Jianshi Tang

IPC: H01L29/06 ,  H01L51/10 ,  H01L51/00 ,  H01L51/05

Abstract: A method for manufacturing a semiconductor device includes forming a first dielectric layer on a substrate, forming a carbon nanotube (CNT) layer on the first dielectric layer, forming a second dielectric layer on the carbon nanotube (CNT) layer, patterning a plurality of trenches in the second dielectric layer exposing corresponding portions of the carbon nanotube (CNT) layer, forming a plurality of contacts respectively in the plurality of trenches on the exposed portions of the carbon nanotube (CNT) layer, performing a thermal annealing process to create end-bonds between the plurality of the contacts and the carbon nanotube (CNT) layer, and depositing a passivation layer on the plurality of the contacts and the second dielectric layer.