公开(公告)号：US10424653B1

公开(公告)日：2019-09-24

申请号：US15984567

申请日：2018-05-21

Applicant: International Business Machines Corporation

Inventor： Chen Zhang ,  Kangguo Cheng ,  Xin Miao ,  Wenyu Xu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8238 ,  H01L29/786

Abstract: A method for fabricating a semiconductor structure includes the following steps. A plurality of dielectric layers is formed on a substrate, wherein the material composition and layer positioning of each of the plurality of dielectric layers are selected to enable defined junctions for one or more features of the semiconductor structure. A trench is formed through each of the plurality of dielectric layers to the top of the substrate, wherein the height and width dimensions of the trench are selected in accordance with an aspect ratio trapping process. A vertical fin structure is formed by epitaxially growing material within the trench on the top of the substrate. In further steps, gate stack and source/drain regions are formed around the vertical fin structure in accordance with the positioning of the plurality of dielectric layers. The resulting semiconductor structure, in one or more examples, is a vertical transport field-effect transistor.

公开(公告)号：US10388731B2

公开(公告)日：2019-08-20

申请号：US15925051

申请日：2018-03-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries Inc.

Inventor： Kangguo Cheng ,  Xin Miao ,  Ruilong Xie ,  Tenko Yamashita

IPC: B82Y10/00 ,  H01L21/02 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265 ,  H01L27/092 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/8238

Abstract: A method of making a nanowire device includes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire stack over the substrate, the second nanowire stack including alternating layers of the first and second semiconducting materials, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack; oxidizing a portion of the first nanowire stack within the first gate spacer; and removing the first semiconducting material from the first nanowire stack and the second nanowire stack.

公开(公告)号：US20190245083A1

公开(公告)日：2019-08-08

申请号：US15888745

申请日：2018-02-05

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Shogo Mochizuki ,  Jingyun Zhang ,  Xin Miao

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L21/306 ,  H01L21/265

CPC classification number: H01L29/7827 ,  H01L21/26506 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/41741 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66666

Abstract: A self-limiting etch is used to provide a semiconductor base located between a semiconductor substrate and a semiconductor fin. The semiconductor base has an upper portion, a lower portion and a midsection. The midsection has a narrower width than the lower and upper portions. A bottom source/drain structure is grown from surfaces of the semiconductor substrate and the semiconductor base. The bottom source/drain structure has a tip region that contacts the midsection of the semiconductor base. The bottom source/drain structures on each side of the semiconductor fin are in close proximity to each other and they have increased volume. Reduced access resistance may also be achieved since the bottom source/drain structure has increased volume.

公开(公告)号：US10361197B2

公开(公告)日：2019-07-23

申请号：US15612257

申请日：2017-06-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L21/02 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66

Abstract: A method of forming features of a finFET structure includes forming fins on a surface of a substrate. A first liner is formed around each fin and a shallow trench isolation region is formed around each fin. A dopant layer is implanted in each fin. A portion of the shallow trench isolation region is etched from each fin. A first portion of the structure is blocked and the first liner replaced with a second liner in a second portion of the structure.

公开(公告)号：US10354930B2

公开(公告)日：2019-07-16

申请号：US15134916

申请日：2016-04-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zuoguang Liu ,  Xin Miao ,  Chen Zhang

IPC: H01L21/66 ,  G01R27/20 ,  H01L21/8234 ,  H01L29/66

Abstract: A contact resistance test device includes a set of full fins providing channels between a source region and a drain region and a set of partial fins connected to the source region. A gate structure is formed over the set of full fins and set of partial fins. A source contact is connected to the source region. A probe contact is isolated from the source contact and is connected to the source region wherein a voltage measured on the probe contact measures contact resistance when a drain-to-source current is flowing in the set of full fins.

公开(公告)号：US10340364B2

公开(公告)日：2019-07-02

申请号：US15812807

申请日：2017-11-14

Applicant: International Business Machines Corporation

Inventor： Chen Zhang ,  Kangguo Cheng ,  Tenko Yamashita ,  Xin Miao ,  Wenyu Xu

IPC: H01L21/28 ,  H01L21/31 ,  H01L29/40 ,  H01L45/00 ,  H01L21/311 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L21/308 ,  H01L29/78

Abstract: Techniques for increasing Weff VFET devices are provided. In one aspect, a method of forming a fin structure includes: depositing a hardmask onto a substrate; depositing a mandrel material onto the hardmask; patterning the mandrel material along a first direction to form first mandrels; forming first spacers alongside the first mandrels; forming second mandrels in between the first mandrels; pattering the first/second mandrels along a second direction perpendicular to the first direction; forming second spacers, perpendicular to the first spacers, alongside the first/second mandrels; selectively removing the first/second mandrels leaving behind a ladder-shaped pattern formed by the first/second spacers; transferring the ladder-shaped pattern to the hardmask and then to the substrate. A method of forming a VFET device, a VFET fin structure, and a VFET device are also provided.

公开(公告)号：US10340292B2

公开(公告)日：2019-07-02

申请号：US15795454

申请日：2017-10-27

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Juntao Li ,  Zuoguang Liu ,  Xin Miao

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/762 ,  H01L21/84 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L29/161

Abstract: A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer is formed on and in contact with at least a first portion of the strained silicon germanium layer. At least a first exposed portion and a second exposed portion of the strained silicon germanium layer are oxidized. The oxidizing process forms a first oxide region and a second oxide region within the first and second exposed portions, respectively, of the strained silicon germanium.

公开(公告)号：US20190198641A1

公开(公告)日：2019-06-27

申请号：US15850723

申请日：2017-12-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chen Zhang ,  Kangguo Cheng ,  Xin Miao ,  Wenyu Xu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/10

Abstract: A method of forming a vertical fin field effect device is provided. The method includes, forming a vertical fin on a substrate, forming a masking block on the vertical fin, wherein the masking block extends a distance outward from the vertical fin sidewalls and endwalls, and a portion of the substrate surrounding the masking block is exposed. The method further includes removing at least a portion of the exposed portion of the substrate to form a recess and a fin mesa below the vertical fin, removing a portion of the fin mesa to form an undercut recess below an overhanging portion of the masking block, forming a spacer layer on the masking block and in the undercut recess, and removing a portion of the spacer layer to form an undercut spacer in the undercut recess.

公开(公告)号：US20190189781A1

公开(公告)日：2019-06-20

申请号：US16284862

申请日：2019-02-25

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/306 ,  H01L21/02 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/66742 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78696

Abstract: A method for manufacturing a semiconductor device includes forming a stacked configuration of a plurality of silicon germanium layers and a plurality of silicon layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a silicon layer stacked on a silicon germanium layer, patterning the stacked configuration into a plurality of patterned stacks spaced apart from each other, and etching exposed sides of the plurality of silicon germanium layers to remove portions of the silicon germanium layers from lateral sides of each of the plurality of silicon germanium layers, wherein a concentration of germanium is varied between each of the plurality of silicon germanium layers to compensate for variations in etching rates between the plurality of silicon germanium layers to result in remaining portions of each of the plurality of silicon germanium layers having the same or substantially the same width as each other.

公开(公告)号：US20190181220A1

公开(公告)日：2019-06-13

申请号：US15836206

申请日：2017-12-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/20 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/84

Abstract: A method of forming a semiconductor structure is provided. Trenches are formed in a first dielectric layer having a first height on a substrate. First III-V semiconductor patterns including aluminum are formed in the trenches to a second height lower than the first height. Second III-V semiconductor patterns are formed on the first III-V semiconductor patterns to a third height not higher than the first height to form fins including the first and second III-V semiconductor patterns. The first dielectric layer is completely removed to expose the fins. Selective oxidation is performed to oxidize the first III-V semiconductor patterns to form oxidized first III-V semiconductor patterns. Fin patterning is performed. A second dielectric layer is formed to cover the fins. The second dielectric layer is recessed to a level not higher than top surfaces of the oxidized first III-V semiconductor patterns. The semiconductor structure is also provided.