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    Novel tumor necrosis factor receptor homologs and nucleic acids encoding the same
    132.
    发明申请
    Novel tumor necrosis factor receptor homologs and nucleic acids encoding the same 审中-公开
    新型肿瘤坏死因子受体同源物和编码相同的核酸

    公开(公告)号：US20120178163A1

    公开(公告)日：2012-07-12

    申请号：US13345489

    申请日：2012-01-06

    Applicant: Audrey Goddard ,  James Pan ,  Minhong Yan

    Inventor： Audrey Goddard ,  James Pan ,  Minhong Yan

    IPC: C12N5/071

    CPC classification number: C12N15/10 ,  A61K38/00 ,  C07K14/4703 ,  C07K14/4705 ,  C07K14/70578 ,  C12N2799/026 ,  C12Q1/686 ,  C12Q2531/113 ,  C12Q2521/331

    Abstract: The present invention is directed to novel polypeptides having homology to members of the tumor necrosis factor receptor family and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptides molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention and to methods for producing the polypeptides of the present invention.

    Abstract translation: 本发明涉及与肿瘤坏死因子受体家族的成员具有同源性的新型多肽和编码那些多肽的核酸分子。 本文还提供了包含这些核酸序列的载体和宿主细胞，包含与异源多肽序列融合的本发明多肽的嵌合多肽分子，与本发明的多肽结合的抗体以及本发明的多肽的制备方法 发明。

    Structure and method for forming field effect transistor with low resistance channel region
    133.
    发明授权
    Structure and method for forming field effect transistor with low resistance channel region 有权
    用于形成具有低电阻通道区域的场效应晶体管的结构和方法

    公开(公告)号：US07943993B2

    公开(公告)日：2011-05-17

    申请号：US12891616

    申请日：2010-09-27

    Applicant: James Pan ,  Qi Wang

    Inventor： James Pan ,  Qi Wang

    IPC: H01L29/78

    CPC classification number: H01L29/165 ,  H01L21/26506 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66712 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813

    Abstract: A trench-gate field effect transistor includes trenches extending into a silicon region of a first conductivity type, and a gate electrodes in each trench. Body regions of second conductivity type extend over the silicon region between adjacent trenches. Each body region forms a PN junction with the silicon region. A gate dielectric layer lines at least upper sidewalls of each trench, and insulates the gate electrode from the body region. Source regions of the first conductivity flank the trenches. A silicon-germanium region vertically extends through each source region and through a corresponding body region, and terminates within the corresponding body region before reaching the PN junction.

    Abstract translation: 沟槽栅场效应晶体管包括延伸到第一导电类型的硅区域的沟槽和每个沟槽中的栅电极。 第二导电类型的主体区域延伸在相邻沟槽之间的硅区域上。 每个体区与硅区形成PN结。 栅极电介质层至少在每个沟槽的上侧壁布线，并且使栅电极与身体区域绝缘​​。 沟槽侧面的第一导电体的源极区域。 硅 - 锗区域垂直延伸穿过每个源极区域并穿过对应的主体区域，并且在到达PN结点之前终止于相应的体区域内。

    Resonant Cavity Complementary Optoelectronic Transistors
    134.
    发明申请
    Resonant Cavity Complementary Optoelectronic Transistors 有权
    谐振腔互补光电晶体管

    公开(公告)号：US20100296540A1

    公开(公告)日：2010-11-25

    申请号：US12470566

    申请日：2009-05-22

    Applicant: James Pan

    Inventor： James Pan

    IPC: H01S5/00 ,  H01L33/00

    CPC classification number: H01S5/0261 ,  H01L27/15 ,  H01S5/0262

    Abstract: The CMOS field effect transistors, used in microprocessors and other digital VLSI circuits, face major challenges such as thin gate dielectrics leakage and scaling limits, severe short channel effects, limited performance improvement with scaling, complicated fabrication process with added special techniques, and surface mobility degradation. This disclosure proposes a new CMOS-compatible optoelectronic transistor. The current is much higher than the MOS transistors, due to the high carrier mobility with bulk transportation. The optoelectronic transistors are scalable to the sub-nanometer ranges without short channel effects. It is also suitable for low power applications and ULSI circuits. The new transistor consists of a laser or LED diode as drain or source, and a photo sensor diode (avalanche photo diode) as source or drain. The transistor is turned on by applying a gate voltage, similar to the CMOS transistors, and a laser or LED light signal is sent to the nearby photo diode, causing an avalanche breakdown and high drain current. The transistor is surrounded by dielectrics and metal isolations, which serve as a metal box or cavity, so the generated laser or LED lights are confined and reflected back from the metal. The drain current increases exponentially with the drain or gate voltage. This exponential drain current vs. drain or gate voltage characteristics makes the optoelectronic transistor run much faster than the transitional linear MOSFET.The optic transistor current-voltage characteristics are totally different from transitional CMOS transistors.

    Abstract translation: 在微处理器和其他数字VLSI电路中使用的CMOS场效应晶体管面临诸如薄栅极电介质泄漏和结垢限制，严重的短沟道效应，缩放的有限性能改进，附加特殊技术的复杂制造工艺和表面迁移率等主要挑战 降解。 本公开提出了一种新的兼容CMOS的光电晶体管。 电流远高于MOS晶体管，这是由于大容量运输的高载流子迁移率。 光电子晶体管可以扩展到亚纳米范围，而没有短信道效应。 它也适用于低功率应用和ULSI电路。 新的晶体管由激光器或LED二极管作为漏极或源极，以及作为源极或漏极的光电二极管（雪崩光电二极管）组成。 通过施加类似于CMOS晶体管的栅极电压来接通晶体管，并且将激光或LED光信号发送到附近的光电二极管，导致雪崩击穿和高漏极电流。 晶体管被电介质和金属隔离物所围绕，它们用作金属盒或空腔，因此产生的激光或LED灯被限制并从金属反射回来。 漏极电流随漏极或栅极电压呈指数增长。 该指数漏极电流与漏极或栅极电压特性使得光电晶体管的运行比过渡线性MOSFET快得多。 光晶体管电流 - 电压特性与过渡CMOS晶体管完全不同。

    Method for Forming Shielded Gate Trench FET with Multiple Channels
    135.
    发明申请
    Method for Forming Shielded Gate Trench FET with Multiple Channels 审中-公开
    用于形成具有多个通道的屏蔽栅沟槽FET的方法

    公开(公告)号：US20100258866A1

    公开(公告)日：2010-10-14

    申请号：US12823037

    申请日：2010-06-24

    Applicant: James Pan

    Inventor： James Pan

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7831

    Abstract: A method of forming a field effect transistor (FET) includes the following steps. A pair of trenches extending into a semiconductor region of a first conductivity type is formed. A shield electrode is formed in a lower portion of each trench. A gate electrode is formed in an upper portion of each trench over but insulated from the shield electrode. First and second well regions of a second conductivity type are formed in the semiconductor region between the pair of trenches such that the first and second well regions are vertically spaced from one another and laterally abut sidewalls of the pair of trenches. The gate electrode and the first shield electrode are formed relative to the first and second well regions such that a channel is formed in each of the first and second well regions when the FET is biased in the on state.

    Abstract translation: 形成场效应晶体管（FET）的方法包括以下步骤。 形成延伸到第一导电类型的半导体区域的一对沟槽。 在每个沟槽的下部形成有屏蔽电极。 栅极电极形成在每个沟槽的上部，而不是与屏蔽电极绝缘。 第二导电类型的第一阱区和第二阱区形成在一对沟槽之间的半导体区域中，使得第一阱区和第二阱区彼此垂直间隔开并横向邻接该对沟槽的侧壁。 栅电极和第一屏蔽电极相对于第一阱区和第二阱区形成，使得当FET被置于导通状态时，在第一阱区和第二阱区中的每一个中形成沟道。

    Structure and method for forming an oscillating MOS transistor and nonvolatile memory
    136.
    发明申请
    Structure and method for forming an oscillating MOS transistor and nonvolatile memory 审中-公开
    用于形成振荡MOS晶体管和非易失性存储器的结构和方法

    公开(公告)号：US20100252876A1

    公开(公告)日：2010-10-07

    申请号：US12418997

    申请日：2009-04-06

    Applicant: James Pan

    Inventor： James Pan

    IPC: H01L29/792 ,  H01L21/336

    CPC classification number: H01L29/792 ,  H01L21/26586 ,  H01L29/40117 ,  H01L29/42376 ,  H01L29/512 ,  H01L29/66659 ,  H01L29/66833 ,  H01L29/7835

    Abstract: With simply applying the gate voltage, the transistor will start sending out oscillating signals, working like a semiconductor “engine”. A special MOS field effect transistor (FET) includes an extended lightly doped drain and an intrinsic undoped or very lightly doped “gap” between the gate and the heavily doped source. The gap needs to be specially engineered so that the transistor is not always turned on by the MOSFET gate voltage, but will be turned on by the carriers from the forward-biased channel-drain junction diode. Oscillation occurs to the drain current (or voltage) when a suitable gate voltage is applied, due to the repeated back and forth actions of deep depletion in the transistor well and forward bias of the drain-well p-n junction diode. By forming a second spacer gate on one side of the main gate, the device can be used as a non-volatile memory, with the charges stored at the dielectrics / silicon interface, which can significantly impact the oscillating for the READ operation of a memory. This device can also be a frequency amplifier.

    Abstract translation: 通过简单地施加栅极电压，晶体管将开始发送振荡信号，像半导体“引擎”一样工作。 特殊的MOS场效应晶体管（FET）包括扩散的轻掺杂漏极和在栅极和重掺杂源之间的本征未掺杂或非常轻掺杂的“间隙”。 间隙需要进行专门设计，使得晶体管不总是被MOSFET栅极电压导通，而是由来自正向偏置沟道 - 漏极结二极管的载流子导通。 由于在晶体管阱中的深度耗尽和漏阱p-n结二极管的正向偏置的反复来回动作，因此施加合适的栅极电压时，漏极电流（或电压）发生振荡。 通过在主栅极的一侧上形成第二间隔栅极，该器件可以用作非易失性存储器，其中电荷存储在电介质/硅界面处，其可以显着影响用于存储器的READ操作的振荡 。 该器件也可以是一个频率放大器。

    UCP5
    138.
    发明申请
    UCP5 审中-公开

    公开(公告)号：US20080312417A1

    公开(公告)日：2008-12-18

    申请号：US12012569

    申请日：2008-02-04

    Applicant: Sean Adams ,  James Pan

    Inventor： Sean Adams ,  James Pan

    IPC: C07K16/18

    CPC classification number: C07K14/47 ,  C07K2319/00

    Abstract: The present invention is directed to novel polypeptides having homology to certain human uncoupling proteins (“UCPs”) and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention, and methods for producing the polypeptides of the present invention.

    Abstract translation: 本发明涉及与某些人解偶联蛋白（“UCP”）和编码那些多肽的核酸分子具有同源性的新型多肽。 本文还提供了包含那些核酸序列的载体和宿主细胞，包含与异源多肽序列融合的本发明多肽的嵌合多肽分子，与本发明的多肽结合的抗体，以及本发明多肽的制备方法 发明。

    Methods of forming HSG layers and devices
    139.
    发明授权
    Methods of forming HSG layers and devices 失效
    形成HSG层和器件的方法

    公开(公告)号：US07432152B2

    公开(公告)日：2008-10-07

    申请号：US11425607

    申请日：2006-06-21

    Applicant: Randhir P. S. Thakur ,  James Pan

    Inventor： Randhir P. S. Thakur ,  James Pan

    IPC: H01L21/20

    CPC classification number: H01L28/84 ,  C23C16/045 ,  C23C16/24 ,  C23C16/56 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02664 ,  H01L27/10852 ,  H01L28/90 ,  H01L28/91 ,  Y10S438/964

    Abstract: A polysilicon film is formed with enhanced selectivity by flowing chlorine during the formation of the film. The chlorine acts as an etchant to insulative areas adjacent polysilicon structures on which the film is desired to be formed. Bottom electrodes for capacitors are formed using this process, followed by an anneal to create hemishperical grain (HSG) polysilicon. Multilayer capacitor containers are formed in a non-oxidizing ambient so that no oxide is formed between the layers. The structure formed is planarized to form separate containers made from doped and undoped amorphous silicon layers. Selected ones of undoped layers are seeded in a chlorine containing environment and annealed to form HSG. A dielectric layer and second electrode are formed to complete the cell capacitor.

    Abstract translation: 通过在膜的形成期间流动氯，形成具有增强的选择性的多晶硅膜。 氯作为蚀刻剂，其邻近多晶硅结构的绝缘区域需要形成薄膜。 使用该工艺形成用于电容器的底部电极，随后进行退火以产生半球形晶粒（HSG）多晶硅。 多层电容器容器形成在非氧化环境中，使得在层之间不形成氧化物。 所形成的结构被平坦化以形成由掺杂和未掺杂的非晶硅层制成的分离的容器。 将选定的未掺杂层接种在含氯环境中并退火以形成HSG。 形成电介质层和第二电极以完成电池电容器。

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