公开(公告)号：US11983423B2

公开(公告)日：2024-05-14

申请号：US17648399

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Jonathan S. Parry

IPC: G06F3/06 ,  G06F1/3234 ,  G06F1/3296

CPC classification number: G06F3/0634 ,  G06F1/3275 ,  G06F1/3296 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673

Abstract: Methods, systems, and devices for host recovery for a stuck condition of a memory system are described. The host system may transmit a first command for the memory system to transition from a first power mode to a second power mode (e.g., low-power mode). In some cases, the host system may transmit a second command for the memory system to exit the second power mode shortly after transmitting the first command. The host system may activate a timer associated with a time-out condition for exiting the second power mode and may determine that a duration indicated by the timer expires. In some examples, the host system may transmit a third command for the memory system to perform a hardware reset operation based on determining that the duration of the timer expires.

公开(公告)号：US11977667B2

公开(公告)日：2024-05-07

申请号：US17524471

申请日：2021-11-11

Applicant: Micron Technology, Inc.

Inventor： Christian M. Gyllenskog ,  Jonathan S. Parry

IPC: G06F21/60 ,  G06F12/02 ,  G06F21/54 ,  G06F21/79 ,  G06F21/10

CPC classification number: G06F21/79 ,  G06F12/0246 ,  G06F12/0253 ,  G06F21/54 ,  G06F21/602 ,  G06F21/107

Abstract: Methods, systems, and devices for purging data from a memory device are described. A memory system may receive, from a host system, a command to write data to an address storing an encryption key in a first portion of the memory system that is configured to store secure information (e.g., a Replay Protected Memory Block). The encryption key may be configured to encrypt data associated with the host system that is stored in a second portion of the memory system. The memory system may then receive an indication of a purge command from the host system. The memory system may execute the purge command by transferring data from the first portion of the memory system to a third portion of the memory system configured to store secure information and erasing the data from the first portion of the memory system.

公开(公告)号：US20240126448A1

公开(公告)日：2024-04-18

申请号：US17967265

申请日：2022-10-17

Applicant: Micron Technology, Inc.

Inventor： Animesh R. Chowdhury ,  Kishore K. Muchherla ,  Nicola Ciocchini ,  Akira Goda ,  Jung Sheng Hoei ,  Niccolo' Righetti ,  Jonathan S. Parry

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0679

Abstract: Apparatuses, systems, and methods for adapting a read disturb scan. One example method can include determining a delay between a first read command and a second read command, incrementing a read count based on the determined delay between the first read command and the second read command, and adapting a read disturb scan rate based on the incremented read count.

公开(公告)号：US11934252B2

公开(公告)日：2024-03-19

申请号：US17648394

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Nadav Grosz ,  Jonathan S. Parry

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3287

CPC classification number: G06F1/3275 ,  G06F1/3287

Abstract: Methods, systems, and devices for shallow hibernate power state are described. A memory system may include a memory array and a controller. The memory system may transition from a first power state having a first current to a second power state having a second current less than the first current, where the first power state is associated with executing received commands and the second power state is associated with deactivating one or more components of the memory array. The memory system may initiate a timer after transitioning from the first power state to the second power state. The memory system may determine the timer satisfies a threshold and transition from the second power state to a third power state having a third current less than the second current based on the timer satisfying the threshold.

公开(公告)号：US11907547B2

公开(公告)日：2024-02-20

申请号：US17729207

申请日：2022-04-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Liang Yu ,  Jonathan S. Parry ,  Xiaojiang Guo

IPC: G06F12/00 ,  G06F3/06 ,  G11C16/32 ,  G06F1/3206 ,  G11C7/22 ,  G11C7/10 ,  G06F1/3215 ,  G11C16/30 ,  G11C5/14 ,  G11C16/04 ,  H01L25/065 ,  G06F119/06

CPC classification number: G06F3/0625 ,  G06F1/3206 ,  G06F1/3215 ,  G06F3/0631 ,  G06F3/0683 ,  G11C5/14 ,  G11C7/1045 ,  G11C7/22 ,  G11C16/30 ,  G11C16/32 ,  G06F2119/06 ,  G11C16/0483 ,  H01L25/0657 ,  H01L2225/06562

Abstract: Memory device might include a controller configured to cause the memory device to determine whether the memory device is waiting to initiate a next phase of an access operation, and in response to determining that the memory device is waiting to initiate the next phase, determine whether there is sufficient available current budget to initiate the next phase in a selected operating mode in response to at least the priority token of the memory device, an expected peak current magnitude for the next phase in the selected operating mode, and additional expected peak current magnitudes for other memory devices. In response to determining that there is sufficient available current budget to initiate the next phase in the selected operating mode, the memory device might output the expected peak current magnitude for the next phase in the selected operating mode from the memory device.

公开(公告)号：US20240055058A1

公开(公告)日：2024-02-15

申请号：US18229249

申请日：2023-08-02

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Liang Yu ,  Jonathan S. Parry

IPC: G11C16/30 ,  G11C5/06

CPC classification number: G11C16/30 ,  G11C5/06

Abstract: A memory die includes a memory array and control logic, operatively coupled with the memory array, to perform operations including receiving a peak power management (PPM) token during a current PPM cycle, in response to receiving the PPM token, determining, based on a set of communication frequencies, whether to communicate auxiliary data to at least one other memory die during the current PPM cycle, wherein each communication frequency of the set of communication frequencies indicates when a respective type of auxiliary data is eligible for communication during a PPM cycle, and in response to determining to communicate auxiliary data to the at least one other memory die, causing a selected type of auxiliary data to be communicated to the at least one other memory die, wherein the selected type of auxiliary data is determined from the set of communication frequencies in view of the current PPM cycle.

公开(公告)号：US20240045596A1

公开(公告)日：2024-02-08

申请号：US17881294

申请日：2022-08-04

Applicant: Micron Technology, Inc.

Inventor： Reshmi Basu ,  Jonathan S. Parry ,  David Aaron Palmer ,  Luca Porzio ,  Giuseppe Cariello ,  Stephen Hanna

IPC: G06F3/06

CPC classification number: G06F3/0617 ,  G06F3/0653 ,  G06F3/0679

Abstract: Methods, systems, and devices for low-power boot-up for memory systems are described. A memory system may be configured to receive, over a first conductive path of a second communication interface, a first indication to boot-up a memory system and a first communication interface associated with the memory system, wherein the first communication interface includes a plurality of conductive paths; receive, over a second conductive path of the second communication interface, a second indication whether to perform a boot-up operation of the memory system using a low-power mode or a high-power mode based at least in part on receiving the first indication; and boot the memory system according to the low-power mode or the high-power mode based at least in part on receiving the second indication.

公开(公告)号：US20230376243A1

公开(公告)日：2023-11-23

申请号：US17747676

申请日：2022-05-18

Applicant: Micron Technology, Inc.

Inventor： Reshmi Basu ,  Jonathan S. Parry

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for storing parity during refresh operations are described. In some examples, refresh operations may be performed on a memory device when the memory device is idle. For example, a refresh operation may entail performing a logical operation on first data and a first set of parity bits and second data and a second set of parity bits. The logical operation may generate a third set of parity bits which may be used for data retention purposes. Moreover, during a read operation, the third set of parity bits may be used to recover corrupt or otherwise invalid data in the event of an error.

公开(公告)号：US20230350587A1

公开(公告)日：2023-11-02

申请号：US18137002

申请日：2023-04-20

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Liang Yu ,  Jonathan S. Parry ,  Chulbum Kim ,  Daniel J. Hubbard ,  Suresh Rajgopal

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0658 ,  G06F3/0679

Abstract: A memory device includes memory dies, each memory die including a memory array and control logic, operatively coupled with the memory array, to perform peak power management (PPM) operations. The PPM operations include receiving a request to perform an operation, determining whether to initiate a PPM priority override procedure, and in response to determining to initiate the PPM priority override procedure, performing the PPM priority override procedure to execute the operation. Performing the PPM priority override procedure includes reconfiguring each high current breakpoints as a respective low current breakpoint to execute the operation.

公开(公告)号：US11775422B2

公开(公告)日：2023-10-03

申请号：US17399406

申请日：2021-08-11

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  David Aaron Palmer ,  Giuseppe Cariello

IPC: G06F12/00 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0253 ,  G06F2212/466 ,  G06F2212/7201

Abstract: Methods, systems, and devices for logic remapping techniques are described. A memory system may receive a write command to store information at a first logical address of the memory system. The memory system may generate a first entry of a logical-to-physical mapping that maps the first logical address with a first physical address that stores the information. The memory system may perform a defragmentation operation or other remapping operation. In such a defragmentation operation, the memory system may remap the first logical address to a second logical address, such that the second logical address is mapped to the first physical address. The memory system may generate a second entry of a logical-to-logical mapping that maps the first logical address with the second logical address.