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131.发明申请公开(公告)号：US20180269904A1
公开(公告)日：2018-09-20
申请号：US15461623
申请日：2017-03-17
Applicant: Micron Technology, Inc.
Inventor： Patrick R. Khayat , Sivagnanam Parthasarathy , Mustafa N. Kaynak
CPC classification number: H03M13/253 , H03M13/152 , H03M13/2909 , H03M13/2948
Abstract: Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include encoding data by including parity data for a number of cross-over bits, wherein the number of cross-over bits are bits located at intersections of column codewords and row codewords.
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公开(公告)号：US20180144791A1
公开(公告)日：2018-05-24
申请号：US15874529
申请日：2018-01-18
Applicant: Micron Technology, Inc.
Inventor： Sivagnanam Parthasarathy , Patrick R. Khayat , Mustafa N. Kaynak
CPC classification number: G11C11/5628 , G06F3/06 , G06F11/102 , G06F11/104 , G06F12/02 , G11C11/5642 , G11C16/0483 , G11C29/16 , G11C2211/5641
Abstract: Apparatuses and methods for determining soft data for fractional digit memory cells are provided. One example apparatus can include a controller to determine states of memory cells of a group of memory cells operated as fractional digit memory cells, and determine soft data based, at least partially, on dimensions to which particular memory cells correspond with respect to the group of memory cells, determined states of the memory cells with respect to a state adjacent a state corresponding to a swapping shell, and whether a particular memory cell is a candidate for swapping.
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公开(公告)号：US20180013451A1
公开(公告)日：2018-01-11
申请号：US15206799
申请日：2016-07-11
Applicant: Micron Technology, Inc.
CPC classification number: H03M13/116 , G06F11/1068 , G11C29/52 , G11C2029/0409 , G11C2029/0411 , H03M13/1128 , H03M13/114 , H03M13/152 , H03M13/2906 , H03M13/2927 , H03M13/3753
Abstract: One example of layer-by-layer error correction can include iteratively error correcting the codeword on a layer-by-layer basis with the first error correction circuit in a first mode and determining on the layer-by-layer basis whether a number of parity errors in a particular layer is less than a threshold number of parity errors. The codeword can be transferred to a second error correction circuit when the number of parity errors is less than the threshold number of parity errors. The codeword can be iteratively error corrected with the first error correction circuit in a second mode when the number of parity errors is at least the threshold number of parity errors. The threshold number of parity errors can be at least partially based on an adjustable code rate of the first error correction circuit or the second error correction circuit.
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公开(公告)号：US20170300377A1
公开(公告)日：2017-10-19
申请号：US15099675
申请日：2016-04-15
Applicant: Micron Technology, Inc.
Inventor： Mustafa N. Kaynak , Patrick R. Khayat , Sivagnanam Parthasarathy
CPC classification number: G11C16/26 , G06F11/1012 , G11C16/0483 , G11C29/021 , G11C29/028 , G11C29/52 , G11C2029/0411 , H03M13/1102 , H03M13/1111 , H03M13/13 , H03M13/3738 , H03M13/45
Abstract: The present disclosure includes apparatuses and methods for monitoring error correction operations performed in memory. A number of embodiments include a memory and circuitry configured to determine a quantity of erroneous data corrected during an error correction operation performed on soft data associated with a sensed data state of a number of memory cells of the memory, determine a quality of soft information associated with the erroneous data corrected during the error correction operation performed on the soft data, and determine whether to take a corrective action on the sensed data based on the quantity of the erroneous data corrected during the error correction operation and the quality of the soft information associated with the erroneous data corrected during the error correction operation.
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公开(公告)号：US09685243B2
公开(公告)日：2017-06-20
申请号：US15231349
申请日：2016-08-08
Applicant: Micron Technology, Inc.
Inventor： Sivagnanam Parthasarathy , Patrick R. Khayat , Mustafa N. Kaynak
CPC classification number: G11C29/52 , G06F11/1072 , G11C11/5642 , G11C16/26 , G11C16/3454 , G11C16/349 , G11C2029/0411
Abstract: Apparatuses and methods involving the determination of soft data from hard reads are provided. One example method can include determining, using a hard read, a state of a memory cell. Soft data is determined based, at least partially, on the determined state.
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Patent Agency Ranking
公开(公告)号：US20160351275A1
公开(公告)日：2016-12-01
申请号：US15231349
申请日：2016-08-08
Applicant: Micron Technology, Inc.
Inventor： Sivagnanam Parthasarathy , Patrick R. Khayat , Mustafa N. Kaynak
CPC classification number: G11C29/52 , G06F11/1072 , G11C11/5642 , G11C16/26 , G11C16/3454 , G11C16/349 , G11C2029/0411
Abstract: Apparatuses and methods involving the determination of soft data from hard reads are provided. One example method can include determining, using a hard read, a state of a memory cell. Soft data is determined based, at least partially, on the determined state.
Abstract translation: 提供了涉及从硬读取确定软数据的装置和方法。 一个示例性方法可以包括确定使用硬读取存储器单元的状态。 至少部分地基于所确定的状态来确定软数据。
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公开(公告)号：US09391645B2
公开(公告)日：2016-07-12
申请号：US14734483
申请日：2015-06-09
Applicant: Micron Technology, Inc.
Inventor： Sivagnanam Parthasarathy , Patrick R. Khayat , Mustafa N. Kaynak
CPC classification number: H03M13/45 , G06F11/1012 , G06F11/1076 , H03M13/098 , H03M13/1102 , H03M13/1111 , H03M13/13 , H03M13/152 , H03M13/19 , H03M13/2906
Abstract: Apparatuses and methods for determining soft data using a classification code are provided. One example apparatus can include a classification code (CC) decoder and an outer code decoder coupled to the CC decoder. The CC decoder is configured to receive a CC codeword. The CC codeword includes a piece of an outer code codeword and corresponding CC parity digits. The CC decoder is configured to determine soft data associated with the piece of the outer code codeword, at least partially, using the corresponding CC digits.
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公开(公告)号：US09318205B2
公开(公告)日：2016-04-19
申请号：US14626208
申请日：2015-02-19
Applicant: Micron Technology, Inc.
Inventor： Sivagnanam Parthasarathy , Patrick R. Khayat , Mustafa N. Kaynak , Zhenlei Shen
IPC: G06F12/00 , G06F12/06 , G11C16/00 , G11C11/56 , G11C16/10 , G06F12/02 , G11C14/00 , G11C16/04 , G11C13/00
Abstract: The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes: programming a group of G memory cells such that a combination of respective program states of the group maps to a constellation point corresponding to a received N unit data pattern, the group used to store N/G units of data per memory cell; wherein the constellation point is one of a number of constellation points of a constellation associated with mapping respective program state combinations of the group of memory cells to N unit data patterns; and wherein the constellation comprises a first mapping shell and a second mapping shell, the constellation points corresponding to the respective first and second mapping shells determined, at least partially, based on a polynomial expression of order equal to G.
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公开(公告)号：US20150286522A1
公开(公告)日：2015-10-08
申请号：US14747501
申请日：2015-06-23
Applicant: Micron Technology, Inc.
Inventor： Patrick R. Khayat , Sivagnanam Parthasarathy , Mustafa N. Kaynak
CPC classification number: G06F11/0793 , G06F3/0619 , G06F3/0673 , G06F11/0727 , G06F11/0751 , G06F12/06 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3418 , G11C2211/5641
Abstract: The present disclosure includes methods and apparatuses for dual mapping between program states and data patterns. One apparatus includes a memory and a controller configured to control a dual mapping method comprising: performing a base conversion on a received data pattern and mapping a resulting base converted data pattern to one of a first number of program state combinations corresponding to a first group of memory cells; and determining a number of error data units corresponding to the base converted data pattern and mapping the number of error data units to one of a number of second program state combinations corresponding to a second group of memory cells. The number of error data units are mapped to the one of the second number of program state combinations corresponding to the second group of memory cells without being base converted.
Abstract translation: 本公开包括用于在程序状态和数据模式之间进行双重映射的方法和装置。 一种装置包括存储器和控制器，其被配置为控制双映射方法，包括：对所接收的数据模式执行基本转换，并将所得到的基本转换的数据模式映射到对应于第一组的第一组的第一数量的程序状态组合 记忆细胞; 以及确定与所述基本转换的数据模式相对应的错误数据单元的数量，并将所述错误数据单元的数量映射到与第二组存储器单元相对应的多个第二程序状态组合中的一个。 错误数据单元的数量被映射到对应于第二组存储器单元的第二数量的程序状态组合中的一个而不进行基本转换。
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公开(公告)号：US20140244964A1
公开(公告)日：2014-08-28
申请号：US13780499
申请日：2013-02-28
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Patrick R. Khayat , Sivagnanam Parthasarathy , Mustafa N. Kaynak
IPC: G06F12/06
CPC classification number: G06F11/0793 , G06F3/0619 , G06F3/0673 , G06F11/0727 , G06F11/0751 , G06F12/06 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3418 , G11C2211/5641
Abstract: The present disclosure includes methods and apparatuses for dual mapping between program states and data patterns. One apparatus includes a memory and a controller configured to control a dual mapping method comprising: performing a base conversion on a received data pattern and mapping a resulting base converted data pattern to one of a first number of program state combinations corresponding to a first group of memory cells; and determining a number of error data units corresponding to the base converted data pattern and mapping the number of error data units to one of a number of second program state combinations corresponding to a second group of memory cells. The number of error data units are mapped to the one of the second number of program state combinations corresponding to the second group of memory cells without being base converted.
Abstract translation: 本公开包括用于在程序状态和数据模式之间进行双重映射的方法和装置。 一种装置包括存储器和控制器，其被配置为控制双映射方法，包括：对所接收的数据模式执行基本转换，并将所得到的基本转换的数据模式映射到对应于第一组的第一组的第一数量的程序状态组合 记忆细胞; 以及确定与所述基本转换的数据模式相对应的错误数据单元的数量，并将所述错误数据单元的数量映射到与第二组存储器单元相对应的多个第二程序状态组合中的一个。 错误数据单元的数量被映射到对应于第二组存储器单元的第二数量的程序状态组合中的一个而不进行基本转换。
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