公开(公告)号：US09431410B2

公开(公告)日：2016-08-30

申请号：US14069574

申请日：2013-11-01

Applicant: Micron Technology, Inc.

Inventor： Jie Sun ,  Zhenyu Lu ,  Roger W. Lindsay ,  Brian Cleereman ,  John Hopkins ,  Hongbin Zhu ,  Fatma Arzum Simsek-Ege ,  Prasanna Srinivasan ,  Purnima Narayanan

IPC: H01L29/788 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/66825 ,  H01L29/7889

Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.

Abstract translation: 公开了形成一串存储单元的方法，具有一串存储单元的装置和系统。 用于形成一串存储单元的一种这样的方法在衬底上形成源材料。 可以在源材料上形成封盖材料。 可以在封盖材料之上形成选择栅极材料。 多个电荷存储结构可以在选择栅极材料上以多个交替层级的控制栅极和绝缘体材料形成。 可以通过控制栅极和绝缘体材料，选择栅极材料和封盖材料的多个交替层级形成第一开口。 通道材料可以沿着第一开口的侧壁形成。 通道材料的厚度小于第一开口的宽度，使得第二开口由半导体沟道材料形成。

公开(公告)号：US20160049417A1

公开(公告)日：2016-02-18

申请号：US14925589

申请日：2015-10-28

Applicant: Micron Technology, Inc.

Inventor： Charles H. Dennison ,  Akira Goda ,  John Hopkins ,  Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L27/115 ,  H01L29/66

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L27/11578 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

Abstract translation: 垂直存储器中的浮动存储单元。 控制栅极形成在介电材料的第一层和第二层电介质材料之间。 浮动栅极形成在介电材料的第一层和第二层介质材料之间，其中浮动栅极包括朝向控制栅极延伸的突起。 在浮置栅极和控制栅极之间形成电荷阻挡结构，其中电荷阻挡结构的至少一部分围绕突起卷绕。

公开(公告)号：US20150348991A1

公开(公告)日：2015-12-03

申请号：US14824942

申请日：2015-08-12

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Aaron R. Wilson

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/10844 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/4966

Abstract: Some embodiments include a method of fabricating integrated structures. A metal-containing material is formed over a stack of alternating first and second levels. An opening is formed through the metal-containing material and the stack. Repeating vertically-stacked electrical components are formed along the stack at sidewalls of the opening. Some embodiments include a method of forming vertically-stacked memory cells. Metal-containing material is formed over a stack of alternating silicon dioxide levels and conductively-doped silicon levels. A first opening is formed through the metal-containing material and the stack. Cavities are formed to extend into the conductively-doped silicon levels along sidewalls of the first opening. Charge-blocking dielectric and charge-storage structures are formed within the cavities to leave a second opening. Sidewalls of the second opening are lined with gate dielectric and then channel material is formed within the second opening.

Abstract translation: 一些实施例包括制造集成结构的方法。 在交替的第一和第二水平的叠层上形成含金属的材料。 通过含金属材料和叠层形成开口。 在开口的侧壁处沿着堆叠形成重叠的垂直堆叠的电部件。 一些实施例包括形成垂直堆叠的存储单元的方法。 含金属的材料形成在交替的二氧化硅水平和导电掺杂的硅层上。 通过含金属材料和叠层形成第一开口。 腔体形成为延伸到沿着第一开口的侧壁的导电掺杂的硅层中。 电荷阻挡电介质和电荷存储结构形成在空腔内以留下第二开口。 第二开口的侧壁衬有栅极电介质，然后在第二开口内形成通道材料。

公开(公告)号：US08980752B2

公开(公告)日：2015-03-17

申请号：US13948050

申请日：2013-07-22

Applicant: Micron Technology, Inc.

Inventor： Farrell Good ,  Baosuo Zhou ,  Xiaolong Fang ,  Fatma Arzum Simsek-Ege

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/033 ,  H01L21/28 ,  H01L21/3213 ,  H01L27/115 ,  H01L21/302

CPC classification number: H01L21/768 ,  H01L21/0332 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/302 ,  H01L21/32139 ,  H01L27/11521 ,  H01L27/11568

Abstract: A method of forming a plurality of spaced features includes forming sacrificial hardmask material over underlying material. The sacrificial hardmask material has at least two layers of different composition. Portions of the sacrificial hardmask material are removed to form a mask over the underlying material. Individual features of the mask have at least two layers of different composition, with one of the layers of each of the individual features having a tensile intrinsic stress of at least 400.0 MPa. The individual features have a total tensile intrinsic stress greater than 0.0 MPa. The mask is used while etching into the underlying material to form a plurality of spaced features comprising the underlying material. Other implementations are disclosed.

Abstract translation: 形成多个间隔特征的方法包括在下面的材料上形成牺牲性硬掩模材料。 牺牲硬掩模材料具有至少两层不同的组成。 去除部分牺牲硬掩模材料以在下面的材料上形成掩模。 掩模的各个特征具有至少两层不同的组成，其中每个单独特征的层之一具有至少400.0MPa的拉伸内应力。 单个特征具有大于0.0MPa的总拉伸内在应力。 当蚀刻到下面的材料中时，使用掩模以形成包括下面的材料的多个间隔的特征。 公开了其他实现。

公开(公告)号：US20140162418A1

公开(公告)日：2014-06-12

申请号：US13708789

申请日：2012-12-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Saurabh Keshav ,  Scott Pook ,  Fatma Arzum Simsek-Ege

IPC: H01L29/66

CPC classification number: H01L29/66833 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

Abstract: Some embodiments include methods of forming vertically-stacked structures, such as vertically-stacked memory cells. A first hardmask is formed over a stack of alternating electrically conductive levels and electrically insulative levels. A first opening is formed through the first hardmask and the stack. Cavities are formed to extend into the electrically conductive levels. A fill material is formed within the first opening and within the cavities. A second hardmask is formed over the first hardmask and over the fill material. A second opening is formed through the second hardmask. The second opening is narrower than the first opening. The second opening is extended into the fill material to form an upwardly-opening container from the fill material. Sidewalls of the upwardly-opening container are removed, while leaving the fill material within the cavities as a plurality of vertically-stacked structures.

Abstract translation: 一些实施例包括形成垂直堆叠结构的方法，例如垂直堆叠的存储单元。 第一个硬掩模形成在交替导电水平和电绝缘水平的叠层上。 通过第一硬掩模和堆叠形成第一开口。 形成腔以延伸到导电水平。 填充材料形成在第一开口内并在空腔内。 在第一个硬掩模和填充材料上形成第二个硬掩模。 通过第二硬掩模形成第二个开口。 第二个开口比第一个开口窄。 第二开口延伸到填充材料中以从填充材料形成向上开口的容器。 去除向上开口的容器的侧壁，同时将填充材料留在空腔内作为多个垂直堆叠的结构。

公开(公告)号：US12302585B2

公开(公告)日：2025-05-13

申请号：US17805586

申请日：2022-06-06

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Ashonita A. Chavan

IPC: H10B53/30 ,  H10B51/10 ,  H10B51/30 ,  H10B53/10

Abstract: Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, a memory device includes multiple memory cells. Each memory cell may include a bottom electrode having an open top cylinder shape that contains a support pillar, may include a top electrode, may include an insulator that separates the top electrode from the bottom electrode, and may include a leaker device having an open top cylinder shape. A bottom surface of the leaker device may abut at least one of a top surface of the bottom electrode or a top surface of the support pillar. A top surface of the leaker device may abut a bottom surface of a conductive plate. The memory device may also include the conductive plate.

公开(公告)号：US20250133724A1

公开(公告)日：2025-04-24

申请号：US18777342

申请日：2024-07-18

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege

IPC: H10B12/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: A variety of applications can include a memory device having an array of memory cells arranged as hexagonal cells, with each of the memory cells having a gate-all-around (GAA) transistor coupled to a capacitor. Digit lines to the memory cells can be arranged angled relative to the set of access lines at an angle different from ninety degrees. Digit shield lines can be structured between adjacent digit lines. The memory device can be arranged in a wafer-to-wafer interconnect architecture with the array on an array wafer connected to and below a control circuitry wafer in a circuit over array architecture.

公开(公告)号：US20250133721A1

公开(公告)日：2025-04-24

申请号：US18777695

申请日：2024-07-19

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Efe Sinan Ege ,  Haitao Liu

IPC: H10B12/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A variety of applications can include a memory device having an array of memory cells arranged as hexagonal cells, with each of the memory cells having a gate-all-around (GAA) transistor coupled to a capacitor. An access line can be coupled to gates of a first set of multiple GAA transistors of the memory cells. A digit line can be coupled to a second set of multiple GAA transistors of the memory cells, where the digit line is wrapped on a sidewall of an active area of each GAA transistor of the second set. Additional devices and methods are disclosed.

公开(公告)号：US20250133720A1

公开(公告)日：2025-04-24

申请号：US18777396

申请日：2024-07-18

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Efe Sinan Ege

IPC: H10B12/00 ,  G11C11/4091 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A variety of applications can include a memory device having an array of memory cells arranged as hexagonal cells, with each of the memory cells having a gate-all-around (GAA) transistor coupled to a capacitor. An access line can be coupled to gates of a first set of multiple GAA transistors of the memory cells. A digit line can be coupled to a second set of multiple GAA transistors of the memory cells, where the digit line is separated from an adjacent digit line by an airgap. Additional devices and methods are disclosed.

公开(公告)号：US20250061936A1

公开(公告)日：2025-02-20

申请号：US18754884

申请日：2024-06-26

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Haitao Liu

IPC: G11C11/408 ,  G11C11/4091 ,  G11C11/4097 ,  H10B12/00

Abstract: A microelectronic device includes a first die and a second die vertically overlying and attached to the first die. The first die includes an array region and a peripheral region horizontally neighboring the array region. The array region includes memory cells respectively including a first transistor structure, a second transistor structure horizontally neighboring the first transistor structure, and a storage device vertically underlying and coupled to the first transistor structure and the second transistor structure. The peripheral region includes sub word line driver circuitry. The second die includes sense amplifier regions and a CMOS region horizontally neighboring some of the sense amplifier regions. The sense amplifier regions are within a horizontal area of the array region of the first die and include sense amplifier circuitry. The CMOS region horizontally neighbors some of the sense amplifier regions and includes CMOS circuitry. Related memory devices and electronic systems are also described.