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    Apparatuses and methods of reading memory cells based on response to a test pulse
    131.
    发明授权
    Apparatuses and methods of reading memory cells based on response to a test pulse 有权

    公开(公告)号：US10283198B2

    公开(公告)日：2019-05-07

    申请号：US15588301

    申请日：2017-05-05

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer

    IPC: G11C7/00 ,  G11C13/00 ,  G11C11/56

    Abstract: The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to memory arrays and methods of reading memory cells in a memory array, such as a cross point memory array. In one aspect, the method comprises providing a memory array comprising a memory cell in one of a plurality of states. The method additionally comprises determining whether a threshold voltage (Vth) of the memory cell has a value within a predetermined read voltage window. A test pulse is applied to the memory cell if it is determined that the threshold voltage has a value within the predetermined read voltage window. The state of the memory cell may be determined based on a response of the memory cell to the test pulse, wherein the state corresponds to the one of the pluralities of states of the memory cell prior to receiving the test pulse.

    Drift mitigation with embedded refresh
    132.
    发明授权
    Drift mitigation with embedded refresh 有权

    公开(公告)号：US10269442B1

    公开(公告)日：2019-04-23

    申请号：US15857125

    申请日：2017-12-28

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli ,  Agostino Pirovano ,  Andrea Redaelli ,  Fabio Pellizzer ,  Hongmei Wang

    IPC: G11C29/00 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00

    Abstract: Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory cell may be written to by applying a first write voltage and may be subsequently read from by applying a first read voltage of a first polarity. At least one additional (e.g., a second) read voltage—a setback voltage—of a second polarity may be utilized to return the memory cell to its original state. Thus the setback voltage may mitigate a shift in the voltage distribution of the cell caused by the first read voltage.

    APPARATUSES INCLUDING MULTI-LEVEL MEMORY CELLS AND METHODS OF OPERATION OF SAME
    134.
    发明申请
    APPARATUSES INCLUDING MULTI-LEVEL MEMORY CELLS AND METHODS OF OPERATION OF SAME 审中-公开

    公开(公告)号：US20180040370A1

    公开(公告)日：2018-02-08

    申请号：US15231518

    申请日：2016-08-08

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli ,  Russell L. Meyer ,  Agostino Pirovano ,  Andrea Redaelli ,  Lorenzo Fratin ,  Fabio Pellizzer

    IPC: G11C11/56 ,  G11C13/00

    Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.

    APPARATUSES AND METHODS OF READING MEMORY CELLS
    138.
    发明申请
    APPARATUSES AND METHODS OF READING MEMORY CELLS 有权
    读取记忆细胞的装置和方法

    公开(公告)号：US20160247562A1

    公开(公告)日：2016-08-25

    申请号：US14628824

    申请日：2015-02-23

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer ,  Ferdinando Bedeschi

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0047 ,  G11C2013/0057 ,  G11C2213/72

    Abstract: A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (VTH) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (VTH1) of the memory cell and determining whether the VTH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped VTH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (VTH2); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the VTH1 and the VTH2.

    Abstract translation: 即使在第一状态分布和第二状态分布之间的重叠阈值电压（VTH）区域中存在阈值电压，也为读取存储器提供了一种方法。 该方法包括首先对存储器单元上的偏置进行斜坡以确定存储器单元的第一阈值电压（VTH1），并确定VTH1是否在重叠的VTH区域内。 当确定存储器单元位于重叠的VTH区域内时，该方法还包括向存储器单元施加写入脉冲; 第二次使存储器单元上的偏置斜坡以确定第二阈值电压（VTH2）; 以及基于VTH1和VTH2之间的比较，在接收到写脉冲之前确定存储单元的状态。

    CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME
    139.
    发明申请
    CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME 有权
    跨点存储器及其制造方法

    公开(公告)号：US20150243708A1

    公开(公告)日：2015-08-27

    申请号：US14189490

    申请日：2014-02-25

    Applicant: MICRON TECHNOLOGY, INC

    Inventor： Marcello Ravasio ,  Samuele Sciarrillo ,  Fabio Pellizzer ,  Innocenzo Tortorelli ,  Roberto Somaschini ,  Cristina Casellato ,  Riccardo Mottadelli

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2463 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

    Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.

    Abstract translation: 所公开的技术通常涉及集成电路器件，特别涉及交叉点存储器阵列及其制造方法。 在一个方面，一种制造交叉点存储器阵列的方法包括形成存储单元材料堆，所述存储单元材料堆在第一活性材料上包括第一活性材料和第二活性材料，其中第一和第二活性材料之一包括存储材料 并且第一和第二活性材料中的另一个包括选择材料。 制造交叉点阵列的方法还包括对存储单元材料堆叠进行图案化，其包括通过存储单元材料堆叠的第一和第二活性材料中的至少一个的蚀刻，在至少一个的至少一个的侧壁上形成保护衬垫 在蚀刻通过第一和第二活性材料之一之后蚀刻第一和第二活性材料，并且在第一和第二活性材料之一的侧壁上形成保护衬垫之后进一步蚀刻存储单元材料堆叠。

    METHOD, SYSTEM, AND DEVICE FOR PHASE CHANGE MEMORY SWITCH WALL CELL WITH APPROXIMATELY HORIZONTAL ELECTRODE CONTACT
    140.
    发明申请
    METHOD, SYSTEM, AND DEVICE FOR PHASE CHANGE MEMORY SWITCH WALL CELL WITH APPROXIMATELY HORIZONTAL ELECTRODE CONTACT 有权
    用于相位变化的存储器开关壁电路的方法，系统和装置具有大量水平电极接触

    公开(公告)号：US20150188042A1

    公开(公告)日：2015-07-02

    申请号：US14642484

    申请日：2015-03-09

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Fabio Pellizzer ,  Innocenzo Tortorelli

    IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

    CPC classification number: H01L45/1253 ,  G11C13/0004 ,  G11C13/003 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141

    Abstract: Embodiments disclosed herein may include depositing a storage component material over and/or in a trench in a dielectric material, including depositing the storage component material on approximately vertical walls of the trench and a bottom of the trench. Embodiments may also include etching the storage component material so that at least a portion of the storage component material remains on the approximately vertical walls and the bottom of the trench, wherein the trench is contacting an electrode and a selector such that storage component material on the bottom of the trench contacts the electrode.

    Abstract translation: 本文公开的实施例可以包括在介电材料中的和/或沟槽中沉积存储部件材料，包括在沟槽的大致竖直的壁上和沟槽的底部沉积存储部件材料。 实施例还可以包括蚀刻存储部件材料，使得存储部件材料的至少一部分保留在大致垂直的壁和沟槽的底部上，其中沟槽与电极和选择器接触，使得存储部件材料 沟槽底部接触电极。

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