公开(公告)号：US09082962B2

公开(公告)日：2015-07-14

申请号：US14086054

申请日：2013-11-21

Applicant: QUALCOMM Incorporated

Inventor： Seung Hyuk Kang ,  Xia Li ,  Wei-Chuan Chen ,  Kangho Lee ,  Xiaochun Zhu ,  Wah Nam Hsu

IPC: H01L43/12 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: A magnetic tunnel junction (MTJ) with direct contact is manufactured having lower resistances, improved yield, and simpler fabrication. The lower resistances improve both read and write processes in the MTJ. The MTJ layers are deposited on a bottom electrode aligned with the bottom metal. An etch stop layer may be deposited adjacent to the bottom metal to prevent overetch of an insulator surrounding the bottom metal. The bottom electrode is planarized before deposition of the MTJ layers to provide a substantially flat surface. Additionally, an underlayer may be deposited on the bottom electrode before the MTJ layers to promote desired characteristics of the MTJ.

Abstract translation: 具有直接接触的磁性隧道结（MTJ）被制造成具有较低的电阻，提高的产量和更简单的制造。 较低的电阻提高了MTJ中的读取和写入过程。 MTJ层沉积在与底部金属对准的底部电极上。 蚀刻停止层可以沉积在底部金属附近，以防止围绕底部金属的绝缘体的过蚀刻。 在沉积MTJ层之前将底部电极平坦化以提供基本平坦的表面。 另外，可以在MTJ层之前的底部电极上沉​​积底层以促进MTJ的期望特性。

公开(公告)号：US09070870B2

公开(公告)日：2015-06-30

申请号：US14219026

申请日：2014-03-19

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Xia Li ,  Wei-Chuan Chen ,  Seung Hyuk Kang

IPC: H01L21/00 ,  H01L43/12 ,  G11C11/16 ,  H01L43/08 ,  H01L43/10 ,  H01L27/22 ,  H01L41/12 ,  H01F10/32 ,  H01F41/32

CPC classification number: H01L43/12 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1675 ,  H01F10/3254 ,  H01F10/3286 ,  H01F41/325 ,  H01L27/222 ,  H01L41/12 ,  H01L43/08 ,  H01L43/10

Abstract: Partial perpendicular magnetic anisotropy (PPMA) type magnetic random access memory cells are constructed using processes and structural configurations that induce a directed static strain/stress on an MTJ to increase the perpendicular magnetic anisotropy. Consequently, reduced switching current of the MTJ results. The directed static strain/stress on the MTJ is induced in a controlled direction and/or with a controlled magnitude during fabrication. The MTJ is permanently subject to a predetermined directed stress and permanently includes the directed static strain/strain that provides reduced switching current.

Abstract translation: 使用在MTJ上引起定向静态应变/应力以增加垂直磁各向异性的工艺和结构构造来构造部分垂直磁各向异性（PPMA）型磁性随机存取存储器单元。 因此，MTJ的开关电流降低。 在制造过程中，受控方向和/或受控幅度诱发MTJ上的定向静态应变/应力。 MTJ永久地受到预定的定向应力，并且永久地包括提供减小的开关电流的定向静态应变/应变。

公开(公告)号：US20150162405A1

公开(公告)日：2015-06-11

申请号：US14100760

申请日：2013-12-09

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  PR Chidambaram

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/205

CPC classification number: H01L29/1045 ,  H01L21/743 ,  H01L29/1054 ,  H01L29/1087 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/785

Abstract: An apparatus comprises a substrate. The apparatus also comprises a diffusion barrier formed on a surface of a first region of the substrate. The diffusion barrier is formed using a first material having a first band gap energy. The apparatus further comprises a channel region formed on a surface of the diffusion barrier. The channel region is formed using a second material having a second band gap energy that is lower than the first band gap energy. The apparatus further comprises a back gate contact coupled to the first region of the substrate.

Abstract translation: 一种装置包括基板。 该装置还包括形成在基板的第一区域的表面上的扩散阻挡层。 使用具有第一带隙能量的第一材料形成扩散阻挡层。 该装置还包括形成在扩散阻挡层的表面上的沟道区。 沟道区域使用具有低于第一带隙能量的第二带隙能量的第二材料形成。 该装置还包括耦合到衬底的第一区域的背栅极接触。

公开(公告)号：US09047960B2

公开(公告)日：2015-06-02

申请号：US13957460

申请日：2013-08-02

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Zhongze Wang

IPC: G11C16/00 ,  G11C16/10 ,  H01L21/28 ,  H01L29/66 ,  G11C16/14

CPC classification number: G11C16/10 ,  G11C16/0433 ,  G11C16/14 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: An apparatus includes a storage transistor. The storage transistor includes a floating gate configured to store electrical charge and a control gate. The floating gate is coupled to the control gate via capacitive coupling. The floating gate and the control gate are metal. The apparatus also includes an access transistor coupled to the storage transistor. A gate of the access transistor is coupled to a word line. The storage transistor and the access transistor are serially coupled between a bit line and a source line.

Abstract translation: 一种装置包括存储晶体管。 存储晶体管包括被配置为存储电荷的浮动栅极和控制栅极。 浮动栅极通过电容耦合耦合到控制栅极。 浮动门和控制门是金属的。 该装置还包括耦合到存储晶体管的存取晶体管。 存取晶体管的栅极耦合到字线。 存储晶体管和存取晶体管串联耦合在位线和源极线之间。

公开(公告)号：US20150069458A1

公开(公告)日：2015-03-12

申请号：US14021795

申请日：2013-09-09

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Ming Cai ,  Bin Yang

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66977 ,  H01L29/66356 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/7827

Abstract: A tunnel field transistor (TFET) device includes a fin structure that protrudes from a substrate surface. The fin structure includes a base portion proximate to the substrate surface, a top portion, and a first pair of sidewalls extending from the base portion to the top portion. The first pair of sidewalls has a length corresponding to a length of the fin structure. The fin structure also includes a first doped region having a first dopant concentration at the base portion of the fin structure. The fin structure also includes a second doped region having a second dopant concentration at the top portion of the fin structure. The TFET device further includes a gate including a first conductive structure neighboring a first sidewall of the first pair of sidewalls. A dielectric layer electrically isolates the first conductive structure from the first sidewall.

Abstract translation: 隧道场晶体管（TFET）器件包括从衬底表面突出的鳍结构。 翅片结构包括靠近基底表面的基部，顶部和从基部延伸到顶部的第一对侧壁。 第一对侧壁的长度对应于翅片结构的长度。 翅片结构还包括在鳍结构的基部处具有第一掺杂剂浓度的第一掺杂区域。 鳍结构还包括在鳍结构的顶部具有第二掺杂剂浓度的第二掺杂区。 TFET器件还包括栅极，其包括与第一对侧壁的第一侧壁相邻的第一导电结构。 电介质层将第一导电结构与第一侧壁电隔离。

公开(公告)号：US08942034B2

公开(公告)日：2015-01-27

申请号：US13759344

申请日：2013-02-05

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang

IPC: G11C16/04 ,  G11C5/06 ,  G11C7/12 ,  G06F17/50 ,  G11C11/40 ,  G11C17/16 ,  G11C11/404 ,  G11C5/14

CPC classification number: G11C17/18 ,  G06F17/5045 ,  G11C5/06 ,  G11C5/146 ,  G11C7/12 ,  G11C11/40 ,  G11C11/404 ,  G11C11/5692 ,  G11C16/04 ,  G11C17/16 ,  G11C2211/4016

Abstract: A method includes selectively creating a first breakdown condition and a second breakdown condition at a semiconductor transistor structure. The first breakdown condition is between a source overlap region of the semiconductor transistor structure and a gate of the semiconductor transistor structure. The second breakdown condition is between ad rain overlap region of the semiconductor transistor structure and the gate.

Abstract translation: 一种方法包括在半导体晶体管结构中选择性地产生第一击穿条件和第二击穿条件。 第一击穿条件在半导体晶体管结构的源极重叠区域和半导体晶体管结构的栅极之间。 第二击穿条件是在半导体晶体管结构的覆盖区域和栅极之间。

公开(公告)号：US08889431B2

公开(公告)日：2014-11-18

申请号：US13683783

申请日：2012-11-21

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Matthew Nowak ,  Xia Li ,  Seung H. Kang

IPC: H01L43/02 ,  H01F10/32 ,  G11C11/16 ,  H01L27/22 ,  H01L43/12

CPC classification number: H01L43/02 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  H01F10/3254 ,  H01F10/3272 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

Abstract: Magnetic tunnel junctions (MTJs) and methods of forming same are disclosed. A pinned layer is disposed in the MTJ such that a free layer of the MTJ can couple to a drain of an access transistor when provided in a magnetic random access memory (MRAM) bitcell. This structure alters the write current flow direction to align the write current characteristics of the MTJ with write current supply capability of an MRAM bitcell employing the MTJ. As a result, more write current can be provided to switch the MTJ from a parallel (P) to anti-parallel (AP) state. An anti-ferromagnetic material (AFM) layer is provided on the pinned layer to fix pinned layer magnetization. To provide enough area for depositing the AFM layer to secure pinned layer magnetization, a pinned layer having a pinned layer surface area greater than a free layer surface area of the free layer is provided.

Abstract translation: 公开了磁隧道结（MTJ）及其形成方法。 被钉扎层设置在MTJ中，使得当提供在磁性随机存取存储器（MRAM）位单元中时，MTJ的自由层可以耦合到存取晶体管的漏极。 该结构改变写入电流流动方向，以使MTJ的写入电流特性与使用MTJ的MRAM位单元的写入电流供应能力对准。 结果，可以提供更多的写入电流以将MTJ从并行（P）切换到反并行（AP）状态。 在钉扎层上提供反铁磁材料（AFM）层以固定钉扎层的磁化强度。 为了提供足够的用于沉积AFM层以确保钉扎层磁化的区域，提供了具有大于自由层的自由层表面积的钉扎层表面积的钉扎层。

公开(公告)号：US20140264610A1

公开(公告)日：2014-09-18

申请号：US13799955

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Bin Yang ,  Xia Li ,  PR Chidambaram

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/7624 ,  H01L21/765 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0207 ,  H01L29/785

Abstract: Embodiments disclosed in the detailed description include metal oxide semiconductor (MOS) isolation schemes with continuous active areas separated by dummy gates. A MOS device includes an active area formed from a material with a work function that is described as either an n-metal or a p-metal. Active components are formed on this active area using materials having a similar work function. Isolation is effectuated by positioning a dummy gate between the active components. The dummy gate is made from a material having an opposite work function relative to the material of the active area. For example, if the active area was a p-metal material, the dummy gate would be made from an n-metal, and vice versa.

Abstract translation: 在详细描述中公开的实施例包括具有由伪栅极分开的连续有效区域的金属氧化物半导体（MOS）隔离方案。 MOS器件包括由具有作为n金属或p金属的功函数的材料形成的有源区域。 使用具有类似功函数的材料在该有效区域上形成活性组分。 通过在有源部件之间定位一个虚拟栅极来实现隔离。 虚拟门由相对于有源区的材料具有相反功函数的材料制成。 例如，如果有源区域是p金属材料，则虚拟栅极将由n金属制成，反之亦然。

公开(公告)号：US08836079B2

公开(公告)日：2014-09-16

申请号：US13748768

申请日：2013-01-24

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang

IPC: H01L21/02

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L28/88 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Metal-on-Metal (MoM) capacitors having laterally displaced layers and related systems and methods are disclosed. In one embodiment, a MoM capacitor includes a plurality of vertically stacked layers that are laterally displaced relative to one another. Lateral displacement of the layers minimizes cumulative surface process variations making a more reliable and uniform capacitor.

Abstract translation: 公开了具有横向移位层的金属对金属（MoM）电容器及相关系统和方法。 在一个实施例中，MoM电容器包括相对于彼此横向移位的多个垂直堆叠的层。 层的横向位移最小化累积的表面处理变化，从而形成更可靠和更均匀的电容器。

公开(公告)号：US08802452B2

公开(公告)日：2014-08-12

申请号：US13925953

申请日：2013-06-25

Applicant: Qualcomm Incorporated

Inventor： Xia Li ,  Seung H. Kang

IPC: H01L21/28

CPC classification number: G06F17/50 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

Abstract: In a particular embodiment, a method of forming a magnetic tunnel junction (MTJ) device includes forming an MTJ cap layer on an MTJ structure and forming a top electrode layer coupled to the MTJ cap layer. The top electrode layer includes at least two layers and one layer of the two layers includes a nitrified metal.

Abstract translation: 在特定实施例中，形成磁性隧道结（MTJ）器件的方法包括在MTJ结构上形成MTJ覆盖层并形成耦合到MTJ覆盖层的顶部电极层。 顶部电极层包括至少两层，两层的一层包括硝化金属。