公开(公告)号：US07910914B2

公开(公告)日：2011-03-22

申请号：US12018486

申请日：2008-01-23

申请人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kidoh ,  Masaru Kito ,  Mitsuru Sato

发明人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kidoh ,  Masaru Kito ,  Mitsuru Sato

IPC分类号： H01L45/00

CPC分类号： H01L27/101 ,  G11C5/025 ,  G11C5/063 ,  G11C11/1655 ,  G11C11/1659 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/224 ,  H01L27/228 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/147

摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory including: a plurality of memory devices each having: a resistance change element, and a diode connected serially to the resistance change element; and a source conductive layer spreading two-dimensionally to be connected to one ends of the plurality of memory devices.

摘要翻译： 根据本发明的一个方面，提供了一种非易失性半导体存储器，包括：多个存储器件，每个存储器件具有电阻变化元件和串联连接到电阻变化元件的二极管; 以及源极传导层，二维扩展以连接到多个存储器件的一端。

公开(公告)号：US07868315B2

公开(公告)日：2011-01-11

申请号：US12037402

申请日：2008-02-26

申请人： Hiroyasu Tanaka ,  Mitsuru Sato ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Hideaki Aochi

发明人： Hiroyasu Tanaka ,  Mitsuru Sato ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Hideaki Aochi

IPC分类号： H01L29/06

CPC分类号： H01L45/144 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/75 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1675

摘要： A phase change memory device including plural memory cells is disclosed. Each of the memory cells includes memory transistors and phase change film portions formed above or below the memory transistors. The phase change film portions correspond to the respective memory transistors respectively. Vias are provided in order to connect each of the memory transistor in parallel to each of the phase change film portions in each of the memory cells. The vias connect the memory cells in series to one another.

摘要翻译： 公开了一种包括多个存储单元的相变存储器件。 每个存储单元包括形成在存储晶体管的上方或下方的存储晶体管和相变膜部分。 相变膜部分别对应于相应的存储晶体管。 提供通孔，以将存储晶体管中的每一个与每个存储单元中的每个相变膜部分并联连接。 通孔将存储单元串联连接。

公开(公告)号：US20100172189A1

公开(公告)日：2010-07-08

申请号：US12620986

申请日：2009-11-18

申请人： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi ,  Akihiro Nitayama ,  Takashi Maeda ,  Tomoo Hishida

发明人： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi ,  Akihiro Nitayama ,  Takashi Maeda ,  Tomoo Hishida

IPC分类号： G11C16/04 ,  G11C7/06

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30

摘要： A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current.

摘要翻译： 非易失性半导体存储装置包括：包括串联连接的多个存储单元的存储串; 第一选择晶体管，其一端连接到存储器串的一端; 第一布线，其一端连接到第一选择晶体管的另一端; 连接到第一选择晶体管的栅极的第二布线。 控制电路被配置为在保持第一布线的电压大于第二布线的电压一定电位差的同时，在擦除操作中提高第二布线和第一布线的电压。 一定的电位差是导致GIDL电流的电位差。

公开(公告)号：US20080186771A1

公开(公告)日：2008-08-07

申请号：US11896261

申请日：2007-08-30

申请人： Ryota Katsumata ,  Masaru Kito ,  Hideaki Aochi ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Mitsuru Sato

发明人： Ryota Katsumata ,  Masaru Kito ,  Hideaki Aochi ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Mitsuru Sato

IPC分类号： G11C16/06 ,  H01L29/788

CPC分类号： G11C16/24 ,  G11C16/0483 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： In a NAND type flash memory, control electrodes of first select transistors in a plurality memory cell units extending along a data line is integrated to constitute a first select signal line while control electrodes of second select transistor are integrated to constitute a second select signal line. The second select signal line is displaced from the first select signal line by a half pitch.

摘要翻译： 在NAND型闪速存储器中，集成了沿着数据线延伸的多个存储单元单元中的第一选择晶体管的控制电极，以构成第一选择信号线，同时第二选择晶体管的控制电极被积分以构成第二选择信号线 。 第二选择信号线从第一选择信号线移位半个间距。

公开(公告)号：US08338882B2

公开(公告)日：2012-12-25

申请号：US12841662

申请日：2010-07-22

申请人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

发明人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

IPC分类号： H01L29/792

CPC分类号： H01L27/11578 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： According to one embodiment, a semiconductor memory device includes a base, a stacked body, a memory film, a channel body, an interconnection, and a contact plug. The base includes a substrate and a peripheral circuit formed on a surface of the substrate. The stacked body includes a plurality of conductive layers and a plurality of insulating layers alternately stacked above the base. The memory film is provided on an inner wall of a memory hole punched through the stacked body to reach a lowermost layer of the conductive layers. The memory film includes a charge storage film. The interconnection is provided below the stacked body. The interconnection electrically connects the lowermost layer of the conductive layers in an interconnection region laid out on an outside of a memory cell array region and the peripheral circuit. The contact plug pierces the stacked body in the interconnection region to reach the lowermost layer of the conductive layers in the interconnection region.

摘要翻译： 根据一个实施例，半导体存储器件包括基底，堆叠体，存储膜，通道体，互连和接触插塞。 基底包括形成在基片的表面上的基片和外围电路。 堆叠体包括多个导电层和交替堆叠在基底之上的多个绝缘层。 记忆膜设置在通过层叠体冲压的存储孔的内壁上，以到达导电层的最下层。 记忆膜包括电荷存储膜。 互连设置在堆叠体的下方。 互连电连接布置在存储单元阵列区域的外部的互连区域中的导电层的最下层和外围电路。 接触插塞刺穿互连区域中的层叠体到达互连区域中的导电层的最下层。

公开(公告)号：US08253187B2

公开(公告)日：2012-08-28

申请号：US12142289

申请日：2008-06-19

申请人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kido ,  Hideaki Aochi ,  Mitsuru Sato ,  Yasuyuki Matsuoka

发明人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kido ,  Hideaki Aochi ,  Mitsuru Sato ,  Yasuyuki Matsuoka

IPC分类号： H01L27/115

CPC分类号： H01L27/115 ,  H01L27/11556

摘要： A non-volatile semiconductor storage device 10 has a plurality of memory strings 100 with a plurality of electrically rewritable memory transistors MTr1-MTr4 connected in series. The memory string 100 includes a columnar semiconductor CLmn extending in a direction perpendicular to a substrate, a plurality of charge accumulation layers formed around the columnar semiconductor CLmn via insulating films, and selection gate lines on the drain side SGD contacting the columnar semiconductor to configure transistors. The selection gate lines on the drain side SGD have lower selection gate lines on the drain side SGDd, each of which is arranged with an interval with a certain pitch, and upper selection gate lines on the drain side SGDu located on a higher layer than the lower selection gate lines on the drain side SGDd, each of which is arranged on gaps between the lower selection gate lines on the drain side SGDd.

摘要翻译： 非易失性半导体存储装置10具有多个串联连接的多个电可重写存储晶体管MTr1-MTr4的存储器串100。 存储器串100包括沿垂直于衬底的方向延伸的柱状半导体CLmn，经由绝缘膜形成在柱状半导体CLmn周围的多个电荷累积层，以及与柱状半导体接触的漏极侧SGD上的选择栅极线，以配置晶体管 。 漏极侧SGD上的选择栅极线在漏极侧SGDd上具有较低的选择栅极线，每个栅极配置有一定间距的间隔，漏极侧SGDu上的选择栅极线位于高于 漏极侧SGDd上的下部选择栅极线设置在漏极侧SGDd的下部选择栅极线之间的间隙。

公开(公告)号：US20110220987A1

公开(公告)日：2011-09-15

申请号：US12841662

申请日：2010-07-22

申请人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

发明人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： According to one embodiment, a semiconductor memory device includes a base, a stacked body, a memory film, a channel body, an interconnection, and a contact plug. The base includes a substrate and a peripheral circuit formed on a surface of the substrate. The stacked body includes a plurality of conductive layers and a plurality of insulating layers alternately stacked above the base. The memory film is provided on an inner wall of a memory hole punched through the stacked body to reach a lowermost layer of the conductive layers. The memory film includes a charge storage film. The interconnection is provided below the stacked body. The interconnection electrically connects the lowermost layer of the conductive layers in an interconnection region laid out on an outside of a memory cell array region and the peripheral circuit. The contact plug pierces the stacked body in the interconnection region to reach the lowermost layer of the conductive layers in the interconnection region.

摘要翻译： 根据一个实施例，半导体存储器件包括基底，堆叠体，存储膜，通道体，互连和接触插塞。 基底包括形成在基片的表面上的基片和外围电路。 堆叠体包括多个导电层和交替堆叠在基底之上的多个绝缘层。 记忆膜设置在通过层叠体冲压的存储孔的内壁上，以到达导电层的最下层。 记忆膜包括电荷存储膜。 互连设置在堆叠体的下方。 互连电连接布置在存储单元阵列区域的外部的互连区域中的导电层的最下层和外围电路。 接触插塞刺穿互连区域中的层叠体到达互连区域中的导电层的最下层。

公开(公告)号：US20080315296A1

公开(公告)日：2008-12-25

申请号：US12142289

申请日：2008-06-19

申请人： Hiroyasu TANAKA ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kido ,  Hideaki Aochi ,  Mitsuru Sato ,  Yasuyuki Matsuoka

发明人： Hiroyasu TANAKA ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kido ,  Hideaki Aochi ,  Mitsuru Sato ,  Yasuyuki Matsuoka

IPC分类号： H01L27/115 ,  H01L21/8247

CPC分类号： H01L27/115 ,  H01L27/11556

摘要： A non-volatile semiconductor storage device 10 has a plurality of memory strings 100 with a plurality of electrically rewritable memory transistors MTr1-MTr4 connected in series. The memory string 100 includes a columnar semiconductor CLmn extending in a direction perpendicular to a substrate, a plurality of charge accumulation layers formed around the columnar semiconductor CLmn via insulating films, and selection gate lines on the drain side SGD contacting the columnar semiconductor to configure transistors. The selection gate lines on the drain side SGD have lower selection gate lines on the drain side SGDd, each of which is arranged with an interval with a certain pitch, and upper selection gate lines on the drain side SGDu located on a higher layer than the lower selection gate lines on the drain side SGDd, each of which is arranged on gaps between the lower selection gate lines on the drain side SGDd.

摘要翻译： 非易失性半导体存储装置10具有多个串联连接的多个电可重写存储晶体管MTr1-MTr4的存储器串100。 存储器串100包括沿垂直于衬底的方向延伸的柱状半导体CLmn，经由绝缘膜形成在柱状半导体CLmn周围的多个电荷累积层，以及与柱状半导体接触的漏极侧SGD上的选择栅极线，以配置晶体管 。 漏极侧SGD上的选择栅极线在漏极侧SGDd上具有较低的选择栅极线，每个栅极配置有一定间距的间隔，漏极侧SGDu上的选择栅极线位于高于 漏极侧SGDd上的下部选择栅极线设置在漏极侧SGDd的下部选择栅极线之间的间隙。

公开(公告)号：US08786008B2

公开(公告)日：2014-07-22

申请号：US13420745

申请日：2012-03-15

申请人： Megumi Ishiduki ,  Masaru Kidoh ,  Mitsuru Sato ,  Masaru Kito ,  Ryota Katsumata

发明人： Megumi Ishiduki ,  Masaru Kidoh ,  Mitsuru Sato ,  Masaru Kito ,  Ryota Katsumata

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/7926 ,  H01L21/28282 ,  H01L27/11582 ,  H01L29/42344

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes: a first stacked body; a memory film; a first channel body layer provided inside the memory film; an interlayer insulating film provided on the first stacked body; a second stacked body having a select gate electrode layer, and a second insulating layer; a gate insulating film provided on a side wall of a second hole communicating with the first hole and penetrating the second stacked body and the interlayer insulating film in a stacking direction of the second stacked body; and a second channel body layer provided inside the gate insulating film in the second hole. A first pore diameter of the second hole at an upper end of the select gate electrode layer is smaller than a second pore diameter of the second hole at an lower end of the select gate electrode layer.

摘要翻译： 根据一个实施例，一种非易失性半导体存储器件包括：第一层叠体; 记忆膜; 设置在记忆膜内部的第一通道体层; 设置在所述第一层叠体上的层间绝缘膜; 具有选择栅电极层的第二层叠体和第二绝缘层; 栅极绝缘膜，设置在与所述第一孔连通的第二孔的侧壁上，并且在所述第二层叠体的层叠方向上贯通所述第二层叠体和所述层间绝缘膜; 以及设置在第二孔中的栅极绝缘膜内部的第二沟道体层。 选择栅电极层的上端的第二孔的第一孔径比选择栅电极层的下端的第二孔的第二孔径小。

公开(公告)号：US20130056815A1

公开(公告)日：2013-03-07

申请号：US13420745

申请日：2012-03-15

申请人： Megumi ISHIDUKI ,  Masaru Kidoh ,  Mitsuru Sato ,  Masaru Kito ,  Ryota Katsumata

发明人： Megumi ISHIDUKI ,  Masaru Kidoh ,  Mitsuru Sato ,  Masaru Kito ,  Ryota Katsumata

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7926 ,  H01L21/28282 ,  H01L27/11582 ,  H01L29/42344

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes: a first stacked body; a memory film; a first channel body layer provided inside the memory film; an interlayer insulating flm provided on the first stacked body; a second stacked body having a select gate electrode layer, and a second insulating layer; a gate insulating film provided on a side wall of a second hole communicating with the first hole and penetrating the second stacked body and the interlayer insulating flm in a stacking direction of the second stacked body; and a second channel body layer provided inside the gate insulating film in the second hole. A first pore diameter of the second hole at an upper end of the select gate electrode layer is smaller than a second pore diameter of the second hole at an lower end of the select gate electrode layer.

摘要翻译： 根据一个实施例，一种非易失性半导体存储器件包括：第一层叠体; 记忆膜; 设置在记忆膜内部的第一通道体层; 设置在第一层叠体上的层间绝缘膜; 具有选择栅电极层的第二层叠体和第二绝缘层; 栅极绝缘膜，设置在与所述第一孔连通的第二孔的侧壁上，并且在所述第二层叠体的层叠方向上贯通所述第二层叠体和所述层间绝缘膜; 以及设置在第二孔中的栅极绝缘膜内部的第二沟道体层。 选择栅电极层的上端的第二孔的第一孔径比选择栅电极层的下端的第二孔的第二孔径小。