公开(公告)号：US20200098434A1

公开(公告)日：2020-03-26

申请号：US16142386

申请日：2018-09-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Murong Lang ,  Zhenming Zhou ,  Deepanshu Dutta

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565

Abstract: Methods and systems for improving the reliability of data stored within a semiconductor memory are described. One issue with determining stored data states for memory cells within a NAND-type memory is that the voltage at the source end of a NAND string may vary greatly from when a memory cell of the NAND string is program verified to when the memory cell is subsequently read leading to bit errors. To compensate for this variability in the source line voltage, different sensing conditions (e.g., the bit line voltages and/or the sensing times) may be applied during a read operation to different sets of memory cells depending on the source line resistance from the memory cells or on the source line voltage zone assigned to the memory cells.

公开(公告)号：US10580504B2

公开(公告)日：2020-03-03

申请号：US16002836

申请日：2018-06-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Dengtao Zhao ,  Peng Zhang ,  Nan Lu ,  Deepanshu Dutta

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C16/08 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  G11C11/56

Abstract: Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.

公开(公告)号：US10468111B1

公开(公告)日：2019-11-05

申请号：US15967270

申请日：2018-04-30

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C7/00 ,  G11C16/34 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G11C11/56

Abstract: Systems and methods reduce device peak current during a read operation by charging control lines of a first set of memory cells faster than control lines of a second set of memory cells while minimizing the channel gradient formed adjacent to a selected word line to suppress occurrences of an injection read disturb in a sense line channel. For example, a first set of memory cells are in a first location relative to a selected memory cell selected for sensing, and a second set of memory cells are in a second location relative to the selected memory cell. The charge device is configured to charge the first set of memory cells and the second set of memory cells. In some aspects, a rate of charging the first set of memory cells is different from a rate of charging the second set of memory cells.

公开(公告)号：US20190333588A1

公开(公告)日：2019-10-31

申请号：US15967270

申请日：2018-04-30

Applicant: SanDisk Technologies LLC

Inventor： Xiang YANG ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/26

Abstract: Systems and methods reduce device peak current during a read operation by charging control lines of a first set of memory cells faster than control lines of a second set of memory cells while minimizing the channel gradient formed adjacent to a selected word line to suppress occurrences of an injection read disturb in a sense line channel. For example, a first set of memory cells are in a first location relative to a selected memory cell selected for sensing, and a second set of memory cells are in a second location relative to the selected memory cell. The charge device is configured to charge the first set of memory cells and the second set of memory cells. In some aspects, a rate of charging the first set of memory cells is different from a rate of charging the second set of memory cells.

公开(公告)号：US20190318792A1

公开(公告)日：2019-10-17

申请号：US15952752

申请日：2018-04-13

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/04 ,  H01L27/11556 ,  H01L27/11582

Abstract: Apparatuses and techniques are described for optimizing a program operation in a memory device. A storage location stores programing data for each word line, such as a program voltage for a set of memory cells. The set of memory cells may be periodically evaluated to determine updated programming setting(s). In one approach, the evaluation involves repeatedly sensing the set of memory cells between a program pulse and a verify signal in a program loop. The word line voltage can be stepped down to an intermediate voltage, then ramped down at a controlled rate while repeatedly sensing the memory cells, such as to detect an upper or lower tail of a threshold voltage distribution. The position of the tail can indicate a degree of over programming and this information can be used to adjust the programming setting(s) in a subsequent program operation.

公开(公告)号：US20190272871A1

公开(公告)日：2019-09-05

申请号：US15910998

申请日：2018-03-02

Applicant: SanDIsk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/34

Abstract: Apparatuses, systems, and methods are disclosed for adjusting a programming setting such as a programming voltage of a set of non-volatile storage cells, such as an SLC NAND array. The non-volatile storage cells may be arranged into a plurality of word lines. A subset of the non-volatile storage cells may be configured to store a programming setting. An on-die controller may be configured to read the programming setting from the setting subset, and write data to the non-volatile storage cells, using the programming setting. The on-die controller may further be configured to determine that the programming setting causes suboptimal programming of one or more of the non-volatile storage cells, and in response to the determination, store a revised programming setting on the setting subset.

公开(公告)号：US10157680B2

公开(公告)日：2018-12-18

申请号：US15385454

申请日：2016-12-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Xiaochang Miao ,  Deepanshu Dutta

IPC: G11C16/06 ,  G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/08

Abstract: Systems and methods for reducing residual electrons within a NAND string subsequent to performing a sensing operation using the NAND string or during the sensing operation. A middle-out programming sequence may be performed in which memory cell transistors in the middle of the NAND string are programmed and program verified prior to programming and verifying other memory cell transistors towards the drain-side end of the NAND string and/or the source-side end of the NAND string. In one example, for a NAND string with 32 memory cell transistors corresponding with word lines WL0 through WL31 from the source-side end of the NAND string to the drain-side end of the NAND string, the memory cell transistor corresponding with word line WL16 may be programmed and program verified prior to programming the memory cell transistors corresponding with word lines WL15 and WL17.

公开(公告)号：US10068656B2

公开(公告)日：2018-09-04

申请号：US15391006

申请日：2016-12-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Deepanshu Dutta ,  Sarath Puthenthermadam ,  Chris Yip

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G06F3/06

CPC classification number: G11C16/3427 ,  G06F3/0619 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0679 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459

Abstract: A non-volatile memory system implements a multi-pass programming process that includes separately programming groups of memory cells in a common block by performing programming for memory cells that are connected to two adjacent word lines and are part of a first group of memory cells followed by performing programming for other memory cells that are also connected to the two adjacent word lines and are part of a second group of memory cells.

公开(公告)号：US12051468B2

公开(公告)日：2024-07-30

申请号：US17530196

申请日：2021-11-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jiahui Yuan ,  Deepanshu Dutta

IPC: G11C16/14 ,  G11C7/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/14 ,  G11C7/1048 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/102 ,  G11C16/26 ,  G11C16/30

Abstract: Programming a plurality of non-volatile memory cells includes performing a soft erase process during the programming. The soft erase process includes pre-charging channels of the memory cells and performing an erase operation subsequent to the pre-charging while the channels are at one or more elevated voltages at least partially due to the pre-charging.

公开(公告)号：US11961563B2

公开(公告)日：2024-04-16

申请号：US17825321

申请日：2022-05-26

Applicant: SanDisk Technologies LLC

Inventor： Towhidur Razzak ,  Jiahui Yuan ,  Deepanshu Dutta

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  H01L25/065

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3459 ,  H01L25/0657 ,  H01L2225/06562

Abstract: Technology is disclosed herein for a memory system that balances peak Icc with programming speed. A memory system applies voltages to respective word lines during a verify operation that balances peak Icc with programming speed. The voltages for which the ramp rate is controlled include a read pass voltage applied to unselected word lines and a spike voltage applied to the selected word line at the beginning of the verify. The ramp rate of the voltages is slow enough to keep the peak Icc during verify to a target peak Icc regardless of which word line is selected for verify. However, the ramp rate of the voltages to the word lines during verify is fast enough to make use of the target peak Icc in order achieve faster programming. Therefore, the impact on programming time is minimized while staying within the allowed peak Icc.