公开(公告)号：US20140299880A1

公开(公告)日：2014-10-09

申请号：US14309409

申请日：2014-06-19

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Qing Liu ,  Prasanna Khare

IPC: H01L29/10 ,  H01L29/04 ,  H01L29/78

CPC classification number: H01L29/1033 ,  H01L29/04 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78

Abstract: Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.

Abstract translation: 可以在半导体器件区域上形成绝缘层，并以基本上减少或防止下面的沟道区域的蚀刻量的方式进行蚀刻。 可以在栅极区域和半导体器件区域上形成第一绝缘层。 可以在第一绝缘层上形成第二绝缘层。 可以在第二绝缘层上形成第三绝缘层。 可以使用第一蚀刻工艺蚀刻第三绝缘层的一部分。 可以使用与第一蚀刻工艺不同的至少第二蚀刻工艺来蚀刻第三绝缘层的蚀刻部分下方的第一绝缘层和第二绝缘层的一部分。

公开(公告)号：US20140210010A1

公开(公告)日：2014-07-31

申请号：US13754614

申请日：2013-01-30

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Junli Wang

IPC: H01L21/82 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/02112 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/82 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/6681

Abstract: A method for fabricating a finFET device having an insulating layer that insulates the fin from a substrate is described. The insulating layer can prevent leakage current that would otherwise flow through bulk semiconductor material in the substrate. The structure may be fabricated starting with a bulk semiconductor substrate, without the need for a semiconductor-on-insulator substrate. Fin structures may be formed by epitaxial growth, which can improve the uniformity of fin heights in the devices.

Abstract translation: 描述了一种用于制造具有使翅片与基板绝缘的绝缘层的finFET器件的方法。 绝缘层可以防止否则将流过衬底中的体半导体材料的漏电流。 该结构可以由体半导体衬底开始制造，而不需要绝缘体上半导体衬底。 鳍结构可以通过外延生长形成，这可以提高器件中翅片高度的均匀性。

公开(公告)号：US20140151759A1

公开(公告)日：2014-06-05

申请号：US13692632

申请日：2012-12-03

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/20 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/06 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: The presence of a facet or a void in an epitaxially grown crystal indicates that crystal growth has been interrupted by defects or by certain material boundaries. Faceting can be suppressed during epitaxial growth of silicon compounds that form source and drain regions of strained silicon transistors. It has been observed that faceting can occur when epitaxial layers of certain silicon compounds are grown adjacent to an oxide boundary, but faceting does not occur when the epitaxial layer is grown adjacent to a silicon boundary or adjacent to a nitride boundary. Because epitaxial growth of silicon compounds is often necessary in the vicinity of isolation trenches that are filled with oxide, techniques for suppression of faceting in these areas are of particular interest. One such technique, presented herein, is to line the isolation trenches with SiN to provide a barrier between the oxide and the region in which epitaxial growth is intended.

Abstract translation: 在外延生长的晶体中存在小面或空隙，表明晶体生长已被缺陷或某些材料边界中断。 在形成应变硅晶体管的源极和漏极区域的硅化合物的外延生长期间，可以抑制刻面。 已经观察到，当某些硅化合物的外延层相邻于氧化物边界生长时，可以发生刻面，但是当外延层生长在邻近硅边界或与氮化物边界相邻时，不会发生刻面。 因为硅化合物的外延生长通常在填充有氧化物的隔离沟槽附近是必要的，所以在这些区域中抑制刻面的技术是特别有意义的。 本文提出的一种这样的技术是使隔离沟槽与SiN对准，以在氧化物和预期外延生长的区域之间提供阻挡层。

公开(公告)号：US20140084372A1

公开(公告)日：2014-03-27

申请号：US14096563

申请日：2013-12-04

Applicant: International Business Machines Corporation ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMicroelectronics, Inc.

Inventor： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

IPC: H01L29/786 ,  H01L29/06

CPC classification number: H01L21/76879 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/78609

Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

Abstract translation: 形成浅沟槽以延伸到绝缘体上半导体（SOI）层的处理衬底中。 在浅沟槽中形成介质金属氧化物层和氮化硅层的电介质衬垫层，随后沉积浅沟槽隔离填充部分。 介电衬垫堆叠从顶部半导体部分的顶表面上方移除，随后除去介电金属氧化物层的氮化硅衬垫层和上部垂直部分。 横向围绕顶部半导体部分和掩埋绝缘体部分的堆叠的边角填充有氮化硅部分。 随后形成栅极结构和源极/漏极结构。 氮化硅部分或电介质金属氧化物层在形成源极/漏极接触通孔期间用作停止层，从而防止源极/漏极接触通孔结构和处理衬底之间的电短路。

公开(公告)号：US20130049172A1

公开(公告)日：2013-02-28

申请号：US13661722

申请日：2012-10-26

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Nicolas Loubet ,  Qing Liu ,  Sanjay C. Mehta ,  Spyridon Skordas

IPC: H01L23/58 ,  H01L21/20

CPC classification number: H01L29/78603 ,  H01L21/02112 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/76224 ,  H01L21/7624 ,  H01L29/66772

Abstract: An insulating region for a semiconductor wafer and a method of forming same. The insulating region can include a tri-layer structure of silicon oxide, boron nitride and silicon oxide. The insulating region may be used to insulate a semiconductor device layer from an underlying bulk semiconductor substrate. The insulating region can be formed by coating the sides of a very thin cavity with silicon oxide, and filling the remainder of the cavity between the silicon oxide regions with boron nitride.

Abstract translation: 半导体晶片的绝缘区域及其形成方法。 绝缘区域可以包括氧化硅，氮化硼和氧化硅的三层结构。 绝缘区域可以用于使半导体器件层与下面的体半导体衬底绝缘。 绝缘区域可以通过用氧化硅涂覆非常薄的腔体的侧面并且用氮化硼填充氧化硅区域之间的空腔的其余部分来形成。

公开(公告)号：US10943837B2

公开(公告)日：2021-03-09

申请号：US16399808

申请日：2019-04-30

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L27/02 ,  H01L27/06 ,  H01L27/088 ,  H01L29/161 ,  H01L29/423 ,  H01L21/84 ,  H01L21/266 ,  H01L21/265 ,  H01L21/308 ,  H01L29/66

Abstract: An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.

公开(公告)号：US10546856B2

公开(公告)日：2020-01-28

申请号：US14189509

申请日：2014-02-25

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Xiuyu Cai ,  Chun-chen Yeh ,  Ruilong Xie

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L29/45

Abstract: A method for fabricating a CMOS integrated circuit structure and the CMOS integrated circuit structure. The method includes creating one or more n-type wells, creating one or more p-type wells, creating one or more pFET source-drains embedded in each of the one or more n-type wells, creating one or more nFET source-drains embedded in each of the one or more p-type wells, creating a pFET contact overlaying each of the one or more pFET source-drains, and creating an nFET contact overlaying each of the one or more nFET source-drains. A material of each of the one or more pFET source-drains includes silicon doped with a p-type material; a material of each of the one or more nFET source-drains includes silicon doped with an n-type material; a material of each pFET contact includes nickel silicide; and a material of each nFET contact comprises titanium silicide.

公开(公告)号：US10340195B2

公开(公告)日：2019-07-02

申请号：US15813071

申请日：2017-11-14

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/3065 ,  H01L21/308

Abstract: A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level.

公开(公告)号：US20180350808A1

公开(公告)日：2018-12-06

申请号：US16049685

申请日：2018-07-30

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  Prasanna Khare ,  Nicolas Loubet

IPC: H01L27/088 ,  H01L21/225 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L27/0886 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

公开(公告)号：US10134903B2

公开(公告)日：2018-11-20

申请号：US15343021

申请日：2016-11-03

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Xiuyu Cai ,  Chun-chen Yeh ,  Ruilong Xie

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L29/06 ,  H01L29/417

Abstract: A method forms a vertical slit transistor includes raised source, drain, and channel regions in a semiconductor substrate. Two gate electrodes are formed adjacent respective sidewalls of the semiconductor substrate. The method forms dielectric material separating the gate electrodes from the source and drain regions.