公开(公告)号：US10078551B2

公开(公告)日：2018-09-18

申请号：US15384355

申请日：2016-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy Anderson

IPC: G06F11/00 ,  G06F9/312 ,  G06F13/36 ,  G06F12/00 ,  G06F11/10 ,  G06F11/14 ,  G06F9/38 ,  G06F13/38 ,  G06F9/345 ,  G06F9/30 ,  G06F13/40 ,  G06F12/0817

CPC classification number: G06F11/1076 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30141 ,  G06F9/345 ,  G06F9/382 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3881 ,  G06F9/3891 ,  G06F11/00 ,  G06F11/10 ,  G06F11/1405 ,  G06F12/0817 ,  G06F12/0875 ,  G06F12/0897 ,  G06F13/38 ,  G06F13/40 ,  G06F2212/1021 ,  G06F2212/452 ,  G06F2212/60

Abstract: This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence including plural nested loops is specified by a control register. The streaming engine includes an address generator producing addresses of data elements and a steam head register storing data elements next to be supplied as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer. Parity bits are formed upon storage of data in the stream buffer which are stored with the corresponding data. Upon transfer to the stream head register a second parity is calculated and compared with the stored parity. The streaming engine signals a parity fault if the parities do not match. The streaming engine preferably restarts fetching the data stream at the data element generating a parity fault.

公开(公告)号：US10007518B2

公开(公告)日：2018-06-26

申请号：US14327066

申请日：2014-07-09

Applicant: Texas Instruments Incorporated

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Mel Alan Phipps ,  Todd T. Hahn ,  Joseph Zbiciak

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30014 ,  G06F9/30094 ,  G06F9/3012

Abstract: The number of registers required is reduced by overlapping scalar and vector registers. This also allows increased compiler flexibility when mixing scalar and vector instructions. Local register read ports are minimized by restricting read access. Dedicated predicate registers reduces requirements for general registers, and allows reduction of critical timing paths by allowing the predicate registers to be placed next to the predicate unit.

公开(公告)号：US20180173634A1

公开(公告)日：2018-06-21

申请号：US15384345

申请日：2016-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F12/0875 ,  G06F12/0811 ,  G06F9/30

CPC classification number: G06F12/0875 ,  G06F9/30047 ,  G06F9/383 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/10 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/454 ,  G06F2212/6026

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine stores an early address of next to be fetched data elements and a late address of a data element in the stream head register for each of the nested loops. The streaming engine stores an early loop counts of next to be fetched data elements and a late loop counts of a data element in the stream head register for each of the nested loops.

公开(公告)号：US20180173532A1

公开(公告)日：2018-06-21

申请号：US15384451

申请日：2016-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/30 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/0897

CPC classification number: G06F12/0897 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30072 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3822 ,  G06F9/383 ,  G06F9/3853 ,  G06F9/3887 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/1056 ,  G06F2212/452 ,  G06F2212/454 ,  G06F2212/6026 ,  G06F2212/621

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register independently specifies a linear address or a circular address mode for each of the nested loops.

公开(公告)号：US09965278B1

公开(公告)日：2018-05-08

申请号：US15384514

申请日：2016-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F12/00 ,  G06F9/30 ,  G06F12/1009 ,  G06F12/0862 ,  G11C21/00

CPC classification number: G06F12/0862 ,  G06F9/345 ,  G06F9/3552 ,  G06F9/383 ,  G06F12/1009 ,  G06F2212/602

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register specifies a circular address mode for the loop, first and second block size numbers and a circular address block size selection. For a first circular address block size selection the block size corresponds to the first block size number. For a first circular address block size selection the block size corresponds to the first block size number. For a second circular address block size selection the block size corresponds to a sum of the first block size number and the second block size number.

公开(公告)号：US20170153890A1

公开(公告)日：2017-06-01

申请号：US15429205

申请日：2017-02-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Quang Bui ,  Abhijeet A. Chachad ,  Kai Chirca ,  Naveen Bhoria ,  Matthew D. Pierson ,  Daniel Wu ,  Ramakrishnan Venkatasubramanian

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0897

CPC classification number: G06F9/3016 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3822 ,  G06F9/383 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/10 ,  G06F11/1048 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/452 ,  G06F2212/60

Abstract: This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include: a SE to L2 interface that can request 512 bits/cycle from L2; a loose binding between SE and L2 interface, to allow a single stream to peak at 1024 bits/cycle; one-way coherence where the SE sees all earlier writes cached in system, but not writes that occur after stream opens; full protection against single-bit data errors within its internal storage via single-bit parity with semi-automatic restart on parity error.

公开(公告)号：US20170139710A1

公开(公告)日：2017-05-18

申请号：US15384342

申请日：2016-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F9/30 ,  G06F12/0811 ,  G06F12/0875 ,  G06F12/0815 ,  G06F9/38 ,  G06F9/32

CPC classification number: G06F9/30043 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0875 ,  G06F2212/452 ,  G06F2212/621

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer constructed like a cache. The stream buffer cache includes plural cache lines, each includes tag bits, at least one valid bit and data bits. Cache lines are allocated to store newly fetched stream data. Cache lines are deallocated upon consumption of the data by a central processing unit core functional unit. Instructions preferably include operand fields with a first subset of codings corresponding to registers, a stream read only operand coding and a stream read and advance operand coding.

公开(公告)号：US20170132149A1

公开(公告)日：2017-05-11

申请号：US15384625

申请日：2016-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Son H. Tran

IPC: G06F12/1045 ,  G06F12/0862 ,  G06F12/1009 ,  G06F12/0897

CPC classification number: G06F12/1045 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3822 ,  G06F9/383 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/10 ,  G06F11/1048 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/68

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream. An address generator produces virtual addresses of data elements. An address translation unit converts these virtual addresses to physical addresses by comparing the most significant bits of a next address N with the virtual address bits of each entry in an address translation table. Upon a match, the translated address is the physical address bits of the matching entry and the least significant bits of address N. The address translation unit can generate two translated addresses. If the most significant bits of address N+1 match those of address N, the same physical address bits are used for translation of address N+1. The sequential nature of the data stream increases the probability that consecutive addresses match the same address translation entry and can use this technique.

公开(公告)号：US20160124890A1

公开(公告)日：2016-05-05

申请号：US14530266

申请日：2014-10-31

Applicant: Texas Instruments Incorporated

Inventor： David M. Thompson ,  Timothy Anderson ,  Joseph Zbiciak ,  Abhijeet A. Chachad ,  Kai Chirca ,  Matthew D. Pierson

IPC: G06F13/42 ,  G06F13/362

CPC classification number: G06F13/4252 ,  G06F13/362

Abstract: The Multicore Bus Architecture (MBA) protocol includes a novel technique of sharing the same physical channel for all transaction types. Two channels, the Transaction Attribute Channel (TAC) and the Transaction Data Channel (TDC) are used. The attribute channel transmits bus transaction attribute information optionally including a transaction type signal, a transaction ID, a valid signal, a bus agent ID signal, an address signal, a transaction size signal, a credit spend signal and a credit return signal. The data channel connected a data subset of the signal lines of the bus separate from the attribute subset of signal lines the bus. The data channel optionally transmits a data valid signal, a transaction ID signal, a bus agent ID signal and a last data signal to mark the last data of a current bus transaction.

Abstract translation: 多核总线架构（MBA）协议包括一种为所有事务类型共享相同物理通道的新技术。 使用两个通道，交易属性通道（TAC）和交易数据通道（TDC）。 属性信道发送可选地包括交易类型信号，交易ID，有效信号，总线代理ID信号，地址信号，交易大小信号，信用支出信号和信用回报信号的总线交易属性信息。 数据通道连接总线信号线的数据子集，与总线信号线的属性子集分开。 数据信道可选地发送数据有效信号，事务ID信号，总线代理ID信号和最后数据信号，以标记当前总线事务的最后数据。

公开(公告)号：US20150019836A1

公开(公告)日：2015-01-15

申请号：US14327066

申请日：2014-07-09

Applicant: Texas Instruments Incorporated

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Mel Alan Phipps ,  Todd T. Hahn ,  Joseph Zbiciak

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30014 ,  G06F9/30094 ,  G06F9/3012

Abstract: The number of registers required is reduced by overlapping scalar and vector registers. This also allows increased compiler flexibility when mixing scalar and vector instructions. Local register read ports are minimized by restricting read access. Dedicated predicate registers reduces requirements for general registers, and allows reduction of critical timing paths by allowing the predicate registers to be placed next to the predicate unit.

Abstract translation: 所需的寄存器数量通过重叠标量和向量寄存器来减少。 这也允许在混合标量和向量指令时增加编译器的灵活性。 通过限制读取访问来使本地寄存器读取端口最小化。 专用谓词寄存器减少通用寄存器的要求，并允许通过允许将谓词寄存器放置在谓词单元旁边来减少关键定时路径。