公开(公告)号：US20160163819A1

公开(公告)日：2016-06-09

申请号：US14588989

申请日：2015-01-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou

IPC: H01L29/66 ,  H01L29/24 ,  H01L29/161 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/6681 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/823431 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/7856 ,  H01L2029/7858

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a sacrificial mandrel on the substrate, wherein the sacrificial mandrel comprises an indentation; and forming a spacer adjacent to the sacrificial mandrel.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在所述基底上形成牺牲心轴，其中所述牺牲心轴包括凹陷; 以及在牺牲心轴附近形成间隔件。

公开(公告)号：US09324570B1

公开(公告)日：2016-04-26

申请号：US14656721

申请日：2015-03-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou

IPC: H01L21/302 ,  H01L21/311 ,  H01L21/308 ,  H01L29/66 ,  H01L21/033

CPC classification number: H01L21/308 ,  H01L21/0337 ,  H01L21/0338 ,  H01L29/6656 ,  H01L29/66795

Abstract: The present invention provides a method of manufacturing a semiconductor device including using a first photomask to form a sacrificial block on a hard mask layer in a first region, a first dummy pattern on the sacrificial block, a first spacer on sidewalls of the sacrificial block and a second spacer in a second region; using a second photomask to form a feature mask on the first dummy pattern and a fin cutting mask on the second spacer; and performing a fin cutting process to remove a portion of the first dummy pattern, a portion of the sacrificial block underlying the portion of the first dummy pattern and the first spacer to form a feature spacer and to remove a portion of the second spacer without being covered with the fin cutting mask to form a fin spacer.

Abstract translation: 本发明提供一种制造半导体器件的方法，包括使用第一光掩模在第一区域的硬掩模层上形成牺牲块，牺牲块上的第一虚设图案，牺牲块的侧壁上的第一间隔物，以及 第二区域中的第二间隔物; 使用第二光掩模在所述第一虚设图案上形成特征掩模，并且在所述第二间隔物上形成翅片切割掩模; 以及执行翅片切割处理以去除所述第一虚设图案的一部分，所述牺牲块的位于所述第一虚设图案的所述部分之下的部分和所述第一间隔件以形成特征间隔物并且除去所述第二间隔物的一部分而不是 用翅片切割面罩覆盖以形成翅片间隔件。

公开(公告)号：US09318389B1

公开(公告)日：2016-04-19

申请号：US14520342

申请日：2014-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  Yu-Ru Yang ,  En-Chiuan Liou

IPC: H01L21/82 ,  H01L27/08 ,  H01L29/49 ,  H01L29/40 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

Abstract: The present invention provides an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

Abstract translation: 本发明提供一种集成电路，其包括衬底，第一晶体管，第二晶体管和第三晶体管。 第一晶体管具有包括第一底部阻挡层，第一功函数金属层和第一金属层的第一金属栅极。 第二晶体管具有包括第二底部阻挡层，第二功函数金属层和第二金属层的第二金属栅极。 第三晶体管具有包括第三底部阻挡层，第三功函数金属层和第三金属层的第三金属栅极。 第一晶体管，第二晶体管和第三晶体管具有相同的导电类型。 第一底部阻挡层的氮浓度>第二底部阻挡层的氮浓度>第三底部阻挡层的氮浓度。

公开(公告)号：US09305884B1

公开(公告)日：2016-04-05

申请号：US14498217

申请日：2014-09-26

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Teng-Chin Kuo ,  Yi-Ting Chen

IPC: H01L23/544 ,  H01L23/532 ,  H01L21/027 ,  H01L21/311 ,  H01L21/033 ,  H01L21/66

CPC classification number: H01L23/544 ,  G03F7/70633 ,  H01L22/12 ,  H01L22/20 ,  H01L23/53271 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An overlay mark applied to a LELE-type double patterning lithography (DPL) process including a first lithography step, a first etching step, a second lithography step and a second etching step in sequence is described. The overlay mark includes a first x-directional pattern and a first y-directional pattern of a previous layer, second x-directional and y-directional patterns of a current layer defined by the first lithography step, and third x-directional and y-directional patterns of the current layer defined by the second lithography step. The second x-directional patterns and the third x-directional patterns are arranged alternately beside the first x-directional pattern. The second y-directional patterns and the third y-directional patterns are arranged alternately beside the first y-directional pattern.

Abstract translation: 描述了应用于包括第一光刻步骤，第一蚀刻步骤，第二光刻步骤和第二蚀刻步骤的LELE型双重图案化光刻（DPL）工艺的覆盖标记。 覆盖标记包括由第一光刻步骤限定的当前层的先前层，第二x方向和y方向图案的第一x方向图案和第一y方向图案，以及第三x方向和y方向图案， 由第二光刻步骤限定的当前层的方向图案。 第二x方向图案和第三x方向图案交替排列在第一x方向图案旁边。 第二y方向图案和第三y方向图案交替排列在第一y方向图案旁边。

公开(公告)号：US20150294058A1

公开(公告)日：2015-10-15

申请号：US14278296

申请日：2014-05-15

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Yu-Ying Huang ,  Jen-Hsiu Li ,  Mei-Chen Chen ,  Ya-Ling Chen ,  Yi-Jing Wang ,  Chi-Ming Huang

IPC: G06F17/50 ,  H01L21/033

CPC classification number: H01L21/0334 ,  H01L21/0337 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In this disclosure, a mark segmentation method and a method for manufacturing a semiconductor structure applying the same are provided. The mark segmentation method comprises the following steps. First, a plurality of segments having a width WS and separated from each other by a space SS formed on a substrate are identified by a processor. Thereafter, a plurality of marks are set over the segments by the processor. This step comprises: (1) adjusting a width WM of each one of the marks being equal to m(WS+SS)+WS or m(WS+SS)+SS by the processor, wherein m is an integer; and (2) adjusting a space SM of adjacent two of the marks by the processor such that WM+SM=n(WS+SS), wherein n is an integer.

Abstract translation: 在本公开中，提供了一种标记分割方法及其制造应用该半导体结构的方法。 标记分割方法包括以下步骤。 首先，通过处理器识别具有宽度WS并且由形成在基板上的空间SS彼此分离的多个段。 此后，处理器在片段上设置多个标记。 该步骤包括：（1）处理器调整每一个标记的宽度WM等于m（WS + SS）+ WS或m（WS + SS）+ SS，其中m是整数; 和（2）由处理器调整相邻两个标记的空格SM，使得WM + SM = n（WS + SS），其中n是整数。

公开(公告)号：US20150097248A1

公开(公告)日：2015-04-09

申请号：US14549559

申请日：2014-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Jia-Rong Wu

IPC: H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76235 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649

Abstract: The semiconductor structure includes a plurality of first insulators in a substrate, a common insulating layer surrounding the sidewall and the bottom of said first insulators in said substrate, and suspended portions of said substrate on said common insulating layer.

Abstract translation: 半导体结构包括在基板中的多个第一绝缘体，围绕所述基板中的所述第一绝缘体的侧壁和底部的公共绝缘层，以及在所述公共绝缘层上的所述基板的悬置部分。

公开(公告)号：US08951918B2

公开(公告)日：2015-02-10

申请号：US13851113

申请日：2013-03-27

Applicant: United Microelectronics Corp.

Inventor： Chia-Jung Li ,  Chia-Jui Liang ,  Po-Chao Tsao ,  Ching-Ling Lin ,  En-Chiuan Liou

IPC: H01L21/311 ,  H01L21/308

CPC classification number: H01L21/308 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76229

Abstract: A method of fabricating a patterned structure of a semiconductor device is provided. First, a substrate having a first region and a second region is provided. A target layer, a hard mask layer and a first patterned mask layer are then sequentially formed on the substrate. A first etching process is performed by using the first patterned mask layer as an etch mask so that a patterned hard mask layer is therefore formed. Spacers are respectively formed on each sidewall of the patterned hard mask layer. Then, a second patterned mask layer is formed on the substrate. A second etching process is performed to etch the patterned hard mask layer in the second region. After the exposure of the spacers, the patterned hard mask layer is used as an etch mask and an exposed target layer is removed until the exposure of the corresponding substrate.

Abstract translation: 提供一种制造半导体器件的图案化结构的方法。 首先，提供具有第一区域和第二区域的基板。 然后在基板上顺序地形成目标层，硬掩模层和第一图案化掩模层。 通过使用第一图案化掩模层作为蚀刻掩模来执行第一蚀刻工艺，从而形成图案化的硬掩模层。 间隔物分别形成在图案化的硬掩模层的每个侧壁上。 然后，在基板上形成第二图案化掩模层。 执行第二蚀刻工艺以蚀刻第二区域中的图案化硬掩模层。 在间隔物曝光之后，将图案化的硬掩模层用作蚀刻掩模，并且去除曝光的目标层，直到相应的基板的曝光。

公开(公告)号：US20140199837A1

公开(公告)日：2014-07-17

申请号：US13740289

申请日：2013-01-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  En-Chiuan Liou ,  Chih-Sen Huang ,  Po-Chao Tsao

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/76814 ,  H01L21/76855 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor structure having at least a contact plug includes the following steps. At first, at least a transistor and an inter-layer dielectric (ILD) layer are formed on a substrate, and the transistor includes a gate structure and two source/drain regions. Subsequently, a cap layer is formed on the ILD layer and on the transistor, and a plurality of openings that penetrate through the cap layer and the ILD layer until reaching the source/drain regions are formed. Afterward, a conductive layer is formed to cover the cap layer and fill the openings, and a part of the conductive layer is further removed for forming a plurality of first contact plugs, wherein a top surface of a remaining conductive layer and a top surface of a remaining cap layer are coplanar, and the remaining cap layer totally covers a top surface of the gate structure.

Abstract translation: 形成至少具有接触插塞的半导体结构的方法包括以下步骤。 首先，在衬底上形成至少一个晶体管和层间电介质（ILD）层，并且晶体管包括栅极结构和两个源极/漏极区域。 随后，在ILD层和晶体管上形成覆盖层，并且形成穿过覆盖层和ILD层的多个开口直到到达源/漏区。 之后，形成导电层以覆盖盖层并填充开口，并且进一步去除导电层的一部分以形成多个第一接触塞，其中剩余导电层的顶表面和顶表面 剩余的盖层是共面的，剩余的盖层完全覆盖栅极结构的顶表面。

公开(公告)号：US08765591B2

公开(公告)日：2014-07-01

申请号：US14023482

申请日：2013-09-11

Applicant: United Microelectronics Corp.

Inventor： Ssu-I Fu ,  I-Ming Tseng ,  En-Chiuan Liou ,  Cheng-Guo Chen

IPC: H01L21/465

CPC classification number: H01L29/66492 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having at least a dummy gate, a sacrificial layer covering sidewalls of the dummy gate and a dielectric layer exposing a top of the dummy gate formed thereon, forming a sacrificial layer covering sidewalls of the dummy gate on the substrate, forming a dielectric layer exposing a top of the dummy gate on the substrate, performing a first etching process to remove a portion of the sacrificial layer surrounding the top of the dummy gate to form at least a first recess, and performing a second etching process to remove the dummy gate to form a second recess. The first recess and the second recess construct a T-shaped gate trench.

Abstract translation: 制造具有金属栅极的半导体器件的方法包括提供至少具有虚拟栅极的基板，覆盖伪栅极的侧壁的牺牲层和暴露其上形成的伪栅极顶部的电介质层，形成覆盖侧壁的牺牲层 形成在基板上暴露伪栅极的顶部的电介质层，执行第一蚀刻工艺以去除围绕虚拟栅极顶部的牺牲层的一部分，以形成至少第一凹部 ，并执行第二蚀刻处理以去除伪栅极以形成第二凹部。 第一凹部和第二凹部构成T形栅极沟槽。

公开(公告)号：US20140017867A1

公开(公告)日：2014-01-16

申请号：US14023482

申请日：2013-09-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ssu-I Fu ,  I-Ming Tseng ,  En-Chiuan Liou ,  Cheng-Guo Chen

IPC: H01L29/66

CPC classification number: H01L29/66492 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having at least a dummy gate, a sacrificial layer covering sidewalls of the dummy gate and a dielectric layer exposing a top of the dummy gate formed thereon, forming a sacrificial layer covering sidewalls of the dummy gate on the substrate, forming a dielectric layer exposing a top of the dummy gate on the substrate, performing a first etching process to remove a portion of the sacrificial layer surrounding the top of the dummy gate to form at least a first recess, and performing a second etching process to remove the dummy gate to form a second recess. The first recess and the second recess construct a T-shaped gate trench.

Abstract translation: 制造具有金属栅极的半导体器件的方法包括提供至少具有虚拟栅极的基板，覆盖伪栅极的侧壁的牺牲层和暴露其上形成的伪栅极顶部的电介质层，形成覆盖侧壁的牺牲层 形成在基板上暴露伪栅极的顶部的电介质层，执行第一蚀刻工艺以去除围绕虚拟栅极顶部的牺牲层的一部分，以形成至少第一凹部 ，并执行第二蚀刻处理以去除伪栅极以形成第二凹部。 第一凹部和第二凹部构成T形栅极沟槽。