公开(公告)号：US20200144102A1

公开(公告)日：2020-05-07

申请号：US16181354

申请日：2018-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Chun-Wei Yu ,  Yu-Ren Wang ,  Shi-You Liu ,  Shao-Hua Hsu

IPC: H01L21/762 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3115

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A patterned mask layer is formed on a semiconductor substrate. An isolation trench is formed in the semiconductor substrate by removing a part of the semiconductor substrate. A liner layer is conformally formed on an inner sidewall of the isolation trench. An implantation process is performed to the liner layer. The implantation process includes a noble gas implantation process. An isolation structure is at least partially formed in the isolation trench after the implantation process. An etching process is performed to remove the patterned mask layer after forming the isolation structure and expose a top surface of the semiconductor substrate. A part of the liner layer formed on the inner sidewall of the isolation trench is removed by the etching process. The implantation process is configured to modify the etch rate of the liner layer in the etching process.

公开(公告)号：US10607897B2

公开(公告)日：2020-03-31

申请号：US16589032

申请日：2019-09-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Ching-Ling Lin ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Wen-An Liang ,  Chia-Ming Kuo ,  Guan-Wei Huang ,  Yuan-Yu Chung ,  I-Ming Tseng

IPC: H01L21/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/762

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to form a first trench; forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and planarizing the dielectric layer to form a first single diffusion break (SDB) structure.

公开(公告)号：US20200098916A1

公开(公告)日：2020-03-26

申请号：US16172856

申请日：2018-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hsiu Chen ,  Sung-Yuan Tsai ,  Chi-Hsuan Tang ,  Kai-Hsiang Wang ,  Chao-Nan Chen ,  Shi-You Liu ,  Chun-Wei Yu ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L21/265

Abstract: A semiconductor device is disclosed. The semiconductor device comprises a substrate, a gate structure disposed on the substrate, a spacer disposed on the substrate and covering a sidewall of the gate structure, an air gap sandwiched between the spacer and the substrate, and a source/drain region disposed in the substrate and having a faceted surface exposed from the substrate, wherein the faceted surface borders the substrate on a boundary between the air gap and the substrate.

公开(公告)号：US10559655B1

公开(公告)日：2020-02-11

申请号：US16210738

申请日：2018-12-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsu Ting ,  Chia-Ming Kuo ,  Fu-Jung Chuang ,  Chun-Wei Yu ,  Po-Jen Chuang ,  Yu-Ren Wang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/51 ,  H01L21/768 ,  H01L29/78 ,  H01L21/764

Abstract: A semiconductor device comprises at least one gate structure disposed on a substrate; a first dielectric layer disposed on the substrate and contacting an outer sidewall of the at least one gate structure; a second dielectric layer having a L shape disposed on the first dielectric layer and contacting the outer sidewall of the at least one gate structure; an etch stop layer contacting the second dielectric layer, the first dielectric layer and the substrate, wherein the second dielectric layer has an upper portion and a lower portion contacting the upper portion, the upper portion extends along the outer sidewall, the lower portion extends from the outer sidewall to the etch stop layer; and an air gap between the second dielectric layer and the etch stop layer; wherein the first dielectric layer and the lower portion of the second dielectric layer have a same width.

公开(公告)号：US10340268B2

公开(公告)日：2019-07-02

申请号：US15284552

申请日：2016-10-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Kuang-Hsiu Chen ,  Chun-Wei Yu ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L29/51 ,  H01L27/088 ,  H01L21/8234

Abstract: A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. Then, the silicon nitride layer not covered by the first gate electrode is removed to expose part of the first silicon oxide layer. Finally, a first dielectric layer is formed to conformally cover the first silicon oxide layer, the first gate electrode and the first cap layer.

公开(公告)号：US20190006172A1

公开(公告)日：2019-01-03

申请号：US15639381

申请日：2017-06-30

Applicant: United Microelectronics Corp.

Inventor： Hsu Ting ,  Kuang-Hsiu Chen ,  Chun-Wei Yu ,  Keng-Jen Lin ,  Yu-Ren Wang

IPC: H01L21/02

Abstract: A method for processing a semiconductor device is provided. The semiconductor device includes a protruding structure on a substrate, the protruding structure having a nitride spacer at a sidewall, and an epitaxial layer is formed in the substrate adjacent to the protruding structure. The method includes removing the nitride spacer on the protruding structure. Then, a dilute hydrofluoric (DHF) cleaning process is performed over the substrate, wherein a top surficial portion of the epitaxial layer is removed. A standard clean (SC) process is performed over the substrate, wherein a native oxide layer is formed on an expose surface of the epitaxial layer.

公开(公告)号：US10043888B2

公开(公告)日：2018-08-07

申请号：US15391048

申请日：2016-12-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Hui Lin ,  Keng-Jen Lin ,  Yu-Ren Wang

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/3213 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/66545 ,  H01L21/32134 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for forming a semiconductor structure includes the following steps. First, a preliminary structure is provided. The preliminary structure includes a substrate and a plurality of fins formed on the substrate. Then, a first polysilicon layer is formed on the substrate. The first polysilicon layer covers at least portions of the fins. An amorphous silicon layer is formed on the first polysilicon layer.

公开(公告)号：US09966266B2

公开(公告)日：2018-05-08

申请号：US15137010

申请日：2016-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Chueh-Yang Liu ,  Yu-Ren Wang ,  Chun-Wei Yu ,  Kuang-Hsiu Chen ,  Yi-Liang Ye ,  Hsu Ting ,  Neng-Hui Yang

IPC: H01L21/02 ,  H01L21/268 ,  H01L21/67 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/687 ,  H01L29/66

CPC classification number: H01L21/2686 ,  H01L21/02057 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/67051 ,  H01L21/6708 ,  H01L21/67115 ,  H01L21/68785 ,  H01L29/0847 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7834

Abstract: An apparatus for semiconductor wafer treatment includes a wafer holding unit configured to receive a single wafer, at least a solution supply unit configured to apply a solution onto the wafer and an irradiation unit configured to emit irradiation to the wafer. The irradiation unit further includes at least a plurality of first light sources configured to emit irradiation in FIR range and a plurality of second light sources configured to emit irradiation in UV range.

公开(公告)号：US20170179286A1

公开(公告)日：2017-06-22

申请号：US14978409

申请日：2015-12-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Kuang-Hsiu Chen ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/033 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02636 ,  H01L21/0332 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

Abstract: A method for forming a semiconductor device includes steps as follows: Firstly, a semiconductor substrate having a circuit element with at least one spacer formed thereon is provided. Next, an acid treatment is performed on a surface of the spacer. A disposable layer is then formed on the circuit element and the spacer. Thereafter, an etching process is performed to form at least one recess in the semiconductor substrate adjacent to the circuit element. Subsequently, a selective epitaxial growth (SEG) process is performed to form an epitaxial layer in the recess.

公开(公告)号：US09685319B2

公开(公告)日：2017-06-20

申请号：US14805639

申请日：2015-07-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ping-Wei Huang ,  Keng-Jen Lin ,  Yi-Hui Lin ,  Yu-Ren Wang

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/3205 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/32055 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for filling gaps of semiconductor device and a semiconductor device with insulation gaps formed by the same are provided. First, a silicon substrate with plural protruding portions is provided, and the protruding portions are spaced apart from each other by gaps with predetermined depths. A nitride-containing layer is formed above the silicon substrate for covering the protruding portions and surfaces of the gaps as a liner nitride. Then, an amorphous silicon layer is formed on the nitride-containing layer. An insulating layer is formed on the amorphous silicon layer, and the gaps are filled up with the insulating layer.