公开(公告)号：US20230314506A1

公开(公告)日：2023-10-05

申请号：US18186624

申请日：2023-03-20

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GmbH

Inventor： Roberto Colombo ,  Vivek Mohan Sharma

IPC: G01R31/317 ,  G01R31/3185

CPC classification number: G01R31/31721 ,  G01R31/31724 ,  G01R31/318566

Abstract: In an embodiment a processing system includes a reset circuit configured to receive a reset-request signal and one or more further reset-request signals, wherein the one or more further reset-request signals are provided by a processing core, one or more further circuits and/or a terminal of the processing system and to generate a combined reset-request signal by combining the reset-request signal and the one or more further reset-request signals, and a hardware test circuit including for each of the one or more further reset-request signals, a respective first combinational circuit configured to selectively assert the respective further reset-request signal, a second combinational logic circuit configured to selectively mask the combined reset-request signal, and a control circuit configured to repeat operations during a diagnostic phase.

公开(公告)号：US11758707B2

公开(公告)日：2023-09-12

申请号：US17118372

申请日：2020-12-10

Applicant: STMicroelectronics International N.V.

Inventor： Shafquat Jahan Ahmed ,  Kedar Janardan Dhori

IPC: H10B10/00

CPC classification number: H10B10/12 ,  H10B10/18

Abstract: A memory cell including a set of active regions that overlay a set of gate regions to form a pair of cross-coupled inverters. A first active region extends along a first axis. A first gate region extends transversely to the first active region and overlays the first active region to form a first transistor of the pair of cross-coupled inverters. A second gate region extends transversely to the first active region and overlays the first active region to form a second transistor of the pair of cross-coupled inverters. A second active region extends along a second axis and overlays the first gate region to form a third transistor of the pair of cross-coupled inverters. A fourth active region extending along a third axis and overlays a gate region to form a transistor of a read port.

公开(公告)号：US11749343B2

公开(公告)日：2023-09-05

申请号：US17578086

申请日：2022-01-18

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Nitin Chawla ,  Tanmoy Roy ,  Anuj Grover

IPC: G11C13/00 ,  G06F9/50 ,  G11C29/00 ,  G11C29/26 ,  G11C29/44 ,  G06N3/063

CPC classification number: G11C13/004 ,  G06F9/5016 ,  G06N3/063 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069 ,  G11C29/006 ,  G11C29/26 ,  G11C2029/4402 ,  G11C2211/561

Abstract: A memory management circuit stores information indicative of reliability-types of regions of a memory array. The memory management circuitry responds to a request to allocate memory in the memory array to a process by determining a request type associated with the request to allocate memory. Memory of the memory array is allocated to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory array. The memory array may be a shared memory array. The memory array may be organized into rows and columns, and the regions of the memory array may be the rows of the memory array.

公开(公告)号：US11742799B2

公开(公告)日：2023-08-29

申请号：US17750137

申请日：2022-05-20

Applicant: STMicroelectronics International N.V.

Inventor： Kapil Kumar Tyagi

IPC: H03B5/12 ,  H03L5/00 ,  H03K3/03

CPC classification number: H03B5/1265 ,  H03L5/00 ,  H03B2200/003 ,  H03K3/0315

Abstract: A voltage controlled oscillator (VCO) has a VCO core and a tuning bank. The tuning bank includes first and second tuning capacitors. A main switch is coupled between the first and second tuning capacitors. The tuning bank also includes control switches that receive a control signal to selectively activate the tuning bank. The main switch receives a level-shifted control signal to activate the tuning bank.

公开(公告)号：US20230251829A1

公开(公告)日：2023-08-10

申请号：US18134737

申请日：2023-04-14

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Rupesh SINGH

IPC: G06F7/548 ,  H03K3/037 ,  G06F7/544 ,  H03K5/01

CPC classification number: G06F7/548 ,  H03K3/037 ,  G06F7/5443 ,  H03K5/01 ,  H03K2005/00078

Abstract: A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.

公开(公告)号：US11714131B1

公开(公告)日：2023-08-01

申请号：US17699900

申请日：2022-03-21

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Manish Sharma ,  Shiv Kumar Vats ,  Umesh Chandra Srivastava

IPC: G01R31/3185 ,  G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/318533 ,  G01R31/318552 ,  G01R31/3177 ,  G01R31/31725

Abstract: In an embodiment, a method for performing scan testing includes: generating first and second scan clock signals; providing the first and second scan clock signals to first and second scan chains, respectively, where the first and second scan clock signals includes respective first shift pulses when a scan enable signal is asserted, and respective first capture pulses when the scan enable signal is deasserted, where the first shift pulse of the first and second scan clock signals correspond to a first clock pulse of a first clock signal, where the first capture pulse of the first scan clock signal corresponds to a second clock pulse of the first clock signal, and where the first capture pulse of the second scan clock signal corresponds to a first clock pulse of a second clock signal different from the first clock signal.

公开(公告)号：US20230231546A1

公开(公告)日：2023-07-20

申请号：US18151332

申请日：2023-01-06

Applicant: STMicroelectronics International N.V.

Inventor： Aradhana KUMARI

IPC: H03K5/1252 ,  H03K5/135

CPC classification number: H03K5/1252 ,  H03K5/135

Abstract: Provided is a time interleaving circuit to mitigate glitches. A first loading stage outputs first data representative of first serialized data. A second loading stage generates second serialized data. The second loading stage receives the first data output by the first loading stage. In response to the first data having a first state, the time interleaving circuit inverts the second serialized data to generate second data representative of the second serialized data. In response to the first data having a second state, the time interleaving circuit outputting the second data without inverting the second serialized data. Exclusive disjunction logic receives the second data and operates on the first data and the second data to generate output data.

公开(公告)号：US20230206032A1

公开(公告)日：2023-06-29

申请号：US18172979

申请日：2023-02-22

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Giuseppe DESOLI ,  Carmine CAPPETTA ,  Thomas BOESCH ,  Surinder Pal SINGH ,  Saumya SUNEJA

IPC: G06N3/045 ,  G06F16/22 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06F18/21

CPC classification number: G06N3/045 ,  G06F16/2282 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06F18/217

Abstract: Embodiments of an electronic device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and a decompression unit coupled to the reconfigurable stream switch. The decompression unit decompresses encoded kernel data in real time during operation of convolutional neural network.

公开(公告)号：US11687762B2

公开(公告)日：2023-06-27

申请号：US16280991

申请日：2019-02-20

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Surinder Pal Singh ,  Thomas Boesch ,  Giuseppe Desoli

IPC: G06N3/063 ,  G06F17/17 ,  G06N20/00 ,  G06F1/26 ,  G06F17/16 ,  G06N3/045 ,  G06N3/08

CPC classification number: G06N3/063 ,  G06F1/26 ,  G06F17/16 ,  G06F17/175 ,  G06N3/045 ,  G06N3/08 ,  G06N20/00

Abstract: Embodiments of a device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and an arithmetic unit coupled to the reconfigurable stream switch. The arithmetic unit has at least one input and at least one output. The at least one input is arranged to receive streaming data passed through the reconfigurable stream switch, and the at least one output is arranged to stream resultant data through the reconfigurable stream switch. The arithmetic unit also has a plurality of data paths. At least one of the plurality of data paths is solely dedicated to performance of operations that accelerate an activation function represented in the form of a piece-wise second order polynomial approximation.

公开(公告)号：US11687428B2

公开(公告)日：2023-06-27

申请号：US17152901

申请日：2021-01-20

Applicant: STMicroelectronics International N.V.

Inventor： Avneep Kumar Goyal

IPC: G06F11/00 ,  G06F11/263 ,  G06F1/06 ,  G06F11/22

CPC classification number: G06F11/263 ,  G06F1/06 ,  G06F11/2236

Abstract: An apparatus includes a main core processor configured to receive a first signal through a first main buffer, a second signal through a second main buffer, a third signal through a third main buffer and a fourth signal through a fourth main buffer, a shadow core processor configured to receive the first signal through a first shadow buffer, the second signal through a second shadow buffer, the third signal through a third shadow buffer and the fourth signal through a fourth shadow buffer, and a first glitch suppression buffer coupled to a common node of an input of the first main buffer and an input of the first shadow buffer.