公开(公告)号：US20190243796A1

公开(公告)日：2019-08-08

申请号：US15961583

申请日：2018-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Zhan Ping

IPC: G06F13/40 ,  G06F13/16

CPC classification number: G06F13/4068 ,  G06F13/1668 ,  G06F13/4022 ,  G06F2213/0026 ,  H04L67/104

Abstract: A data storage module includes: a circuit chip receiving network packets and translating the network packets received from a host computer to a peripheral component interconnect express (PCIe) packets; a field-programmable grid array (FPGA); and one or more data storage devices storing data received from the host computer over the network packets. The circuit chip is coupled to the FPGA and the one or more data storage devices over a PCIe interface. The FPGA is programmably configured to perform one or more data processing acceleration on the data received from the circuit chip over the PCIe interface.

公开(公告)号：US20190235448A1

公开(公告)日：2019-08-01

申请号：US16370461

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Rajesh Banginwar ,  Ramkumar Jayaraman ,  Nabajit Deka ,  Riccardo Mariani

IPC: G05B9/02 ,  H04L12/40 ,  G06F13/40 ,  G06F9/54

CPC classification number: G05B9/02 ,  G06F9/541 ,  G06F13/4022 ,  G06F2213/0016 ,  G06F2213/0026 ,  G06F2213/0038 ,  H04L12/40 ,  H04L2012/40215 ,  H04L2012/40273

Abstract: Methods and apparatus relating to enhancing diagnostic capabilities of computing systems by combining variable patrolling Application Program Interface (API) and comparison mechanism of variables are described. In one embodiment, a first processor core executes a first instance of a workload to generate a first set of safety variables. A second processor core executes a second instance of the workload to generate a second set of safety variables. A third processor core generates a signal in response to comparison of the first set of safety variables and the second set of safety variables. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190197001A1

公开(公告)日：2019-06-27

申请号：US16201904

申请日：2018-11-27

Applicant: ALIBABA GROUP HOLDING LIMITED

Inventor： Liang HAN ,  Xiaowei JIANG ,  Jian CHEN

IPC: G06F13/40 ,  G06F3/06 ,  G06N3/08

CPC classification number: G06F13/4027 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/28 ,  G06F13/4282 ,  G06F2213/0026 ,  G06F2213/28 ,  G06N3/08

Abstract: The present disclosure provides a processor providing a memory architecture having M-number of processing elements each having at least N-number of processing units and a local memory. The processor comprises a first processing element of the M-number of processing elements comprising a first set of N-number of processing units configured to perform a computing operation, and a first local memory configured to store data utilized by the N-number of processing units. The processor further comprises a data hub configured to receive data from the M-number of processing elements and to provide shared data to each processing element of the M-number of processing elements.

公开(公告)号：US20190188153A1

公开(公告)日：2019-06-20

申请号：US15847671

申请日：2017-12-19

Applicant: Western Digital Technologies, Inc.

Inventor： Shay BENISTY ,  Alon MARCU ,  Ariel NAVON

IPC: G06F12/1081 ,  G06F3/06 ,  G06F13/42

CPC classification number: G06F12/1081 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0679 ,  G06F13/4282 ,  G06F2213/0026

Abstract: Apparatuses and methods of directly accessing a memory space of a storage device by a host are provided. In one embodiment, a method of driverless access of a non-volatile memory of a non-volatile memory device by a host includes initializing a PCIe memory space mapping a portion of the non-volatile memory of the non-volatile memory device to a host memory space. The non-volatile memory is mapped through a PCIe link between the host and the non-volatile memory device. Load/store commands are sent to the PCIe memory space for driverless access. The method further includes negotiating an alignment size of the minimum transaction packet size to complete the load/store commands.

公开(公告)号：US20190145835A1

公开(公告)日：2019-05-16

申请号：US15809148

申请日：2017-11-10

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Piyush Gangadhar JADHAV

IPC: G01K3/00 ,  G06F3/06 ,  G06F13/40 ,  G06F13/42 ,  G01K1/02

CPC classification number: G01K3/005 ,  G01K1/026 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2213/0016 ,  G06F2213/0026 ,  G06F2213/0028

Abstract: Systems and methods for integrated thermal management of storage drives are described. In one embodiment, the storage system device may include a storage enclosure, a plurality of storage drives enclosed in the storage enclosure, and one or more processors in each of the plurality of storage drives. In some cases, the plurality of storage drives may include a first storage drive and a second storage drive. In some embodiments, the one or more processors of the first storage drive may be configured to activate a drive temperature monitor of the first storage drive in response to a manufacturer specific command, detect a temperature event of the first storage drive, and send a notification to the storage enclosure upon detecting the temperature event, the notification indicating the temperature event.

公开(公告)号：US20190073329A1

公开(公告)日：2019-03-07

申请号：US15783424

申请日：2017-10-13

Applicant: LONTIUM SEMICONDUCTOR CORPORATION

Inventor： Cheng TAO ,  Yu CHEN ,  Xi XU ,  Xin ZHU

IPC: G06F13/38 ,  G06F13/42 ,  G06F13/16 ,  G06F5/06 ,  G09G3/20

CPC classification number: G06F13/385 ,  G06F5/065 ,  G06F13/1673 ,  G06F13/4282 ,  G06F2205/067 ,  G06F2213/0026 ,  G06F2213/0042 ,  G09G3/2096 ,  G09G2370/12

Abstract: A bidirectional signal conditioning chip for a USB Type-C cable and a USB Type-C cable are provided. The chip includes a memory, a processor and a transfer driver. The transfer driver is configured to regenerate and transmit a high speed signal; the memory is configured to store a program code; the processor is configured to call the program code, and perform the following operations when the program code is executed: determining a data transmission direction and a type supported by transmitted data of the USB Type-C cable; configuring on-off states of buffers in the transfer driver based on the data transmission direction and the supported type, so that a data output direction of the transfer driver is consistent with the data transmission direction.

公开(公告)号：US20190064879A1

公开(公告)日：2019-02-28

申请号：US16081620

申请日：2016-10-24

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Jeffrey Kevin JEANSONNE ,  Rahul V. LAKDAWALA ,  Roger D. BENSON

IPC: G06F1/16 ,  G06F13/38 ,  G06F13/12

CPC classification number: G06F1/1632 ,  G06F13/126 ,  G06F13/38 ,  G06F13/385 ,  G06F2213/0026 ,  G06F2213/0042

Abstract: In some examples, an electronic device is to receive a configuration setting that is configurable to a first setting to indicate a first mode of operation, and a second setting to indicate a second mode of operation, wherein a feature supported by the first mode of operation is disabled in the second mode of operation; and configure a dock to which the electronic device is connected to operate according to a mode indicated by the configuration setting.

公开(公告)号：US20190042520A1

公开(公告)日：2019-02-07

申请号：US15666122

申请日：2017-08-01

Applicant: LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTD.

Inventor： WILSON VELEZ ,  LUKE D. REMIS ,  MARK E. ANDRESEN

IPC: G06F13/42 ,  G06F12/02

CPC classification number: G06F13/4282 ,  G06F12/0246 ,  G06F13/385 ,  G06F2212/7201 ,  G06F2213/0026

Abstract: Out-of-band management of data drives including receiving, from a user, a control command targeting a data drive communicatively coupled to a backplane, wherein the data drive is communicatively coupled to the computing device via an interconnect bus; generating, based on the control command, an out-of-band command targeting a baseboard management controller (BMC) communicatively coupled to the backplane, wherein the out-of-band command comprises a data drive location identifier; sending the out-of-band command to the BMC, wherein the BMC, in response, identifies the data drive on the backplane using the data drive location identifier and a cable topology table, and performs the out-of-band command on the data drive; and receiving, from the BMC, a first notification that the out-of-band command has been performed on the data drive identified by the data drive location identifier.

公开(公告)号：US20180357187A1

公开(公告)日：2018-12-13

申请号：US15700031

申请日：2017-09-08

Applicant: INTEL CORPORATION

Inventor： Myron D. LOEWEN ,  Andrew W. MORNING-SMITH ,  Anthony M. CONSTANTINE

IPC: G06F13/16 ,  G06F13/40 ,  H04L12/40

CPC classification number: G06F13/1631 ,  G06F13/20 ,  G06F13/4081 ,  G06F2213/0026 ,  G06F2213/0052 ,  H04L12/40169

Abstract: Provided are apparatus, system, and method for positionally aware device management bus address assignment. A presence of a plurality of storage devices is detected on a bus. One of the storage devices detected on the bus is selected. A get identifier command is sent on the bus to all of the storage devices that is only responded to by the selected storage device. A unique identifier is received from the selected storage device over the bus. An address for the selected storage device is assigned and an entry is added to the address mapping to indicate the unique identifier, the assigned address, and a physical location indicator for the selected storage device.

公开(公告)号：US20180329716A1

公开(公告)日：2018-11-15

申请号：US15869902

申请日：2018-01-12

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Yan-Ting JIANG

IPC: G06F9/4401 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F9/4405 ,  G06F9/4411 ,  G06F13/4081 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A method for initializing a peripheral component interconnect express (PCI-E) interface card is provided. The method includes: initializing, by a processing unit in a boot procedure according to a preset first value of a flag, a PCI-E interface card inserted in a PCI-E interface slot by using a first initialization parameter included in a basic input/output system (BIOS) code; setting, by the processing unit in the boot procedure according to the initialized PCI-E interface card, the flag to have the first value or a second value; determining, by the processing unit in the boot procedure, whether the initialized PCI-E interface card needs to be reinitialized; and reinitializing, by the processing unit according to the second value of the set flag when the PCI-E interface card needs to be reinitialized, the PCI-E interface card by using a second initialization parameter included in the BIOS code.