公开(公告)号：US20020171104A1

公开(公告)日：2002-11-21

申请号：US09828289

申请日：2001-04-05

发明人： James S. Cable ,  Eugene F. Lyons ,  Michael A. Stuber ,  Mark L. Burgener

IPC分类号： H01L027/01 ,  H01L027/12 ,  H01L031/0392

CPC分类号： H01L21/86 ,  H01L27/1203

摘要： A method for eliminating the radiation-induced off-state current in the P-channel ultrathin silicon-on-sapphire transistor, by providing a retrograde dopant concentration profile that has the effect of moving the Fermi level at the back of the device away from that part of the bandgap where the interface states are located. When the Fermi level does not swing through this area in any region of operation of the device, subthreshold stretchout of the I-V curves does not occur.

摘要翻译： 一种通过提供逆向掺杂剂浓度分布来消除P沟道超薄蓝宝石硅晶体管中的辐射诱发截止电流的方法，其具有使器件背面的费米能级远离该器件背面的效应。 接口状态所在的带隙的一部分。 当在设备的任何操作区域中费米能级别不通过该区域时，不会发生I-V曲线的亚阈值延伸。

公开(公告)号：US20020149058A1

公开(公告)日：2002-10-17

申请号：US10064305

申请日：2002-07-01

申请人： International Business Machines Corporation

发明人： James A. Culp ,  Jawahar P. Nayak ,  Werner A. Rausch ,  Melanie J. Sherony ,  Steven H. Voldman ,  Noah D. Zamdmer

IPC分类号： H01L027/01 ,  H01L027/12 ,  H01L031/0392

CPC分类号： H01L29/4966 ,  H01L29/1083 ,  H01L29/7835

摘要： A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.

摘要翻译： 半导体芯片包括具有整流接触扩散和非整流接触扩散的半导体衬底。 光晕扩散与整流接触扩散相邻，并且没有晕圈扩散与非整流接触扩散相邻。 整流接触扩散可以是FET的源极/漏极扩散，以提高耐穿透性。 非整流接触扩散可以是FET体接触，横向二极管接触或电阻或电容器接触。 避免使用非整流触点的光圈可以降低串联电阻并提高器件特性。 在具有相邻扩散的光晕的器件的芯片的另一实施例中，没有卤素扩散与横向二极管的整流接触扩散相邻，从而显着地提高了二极管的理想性并增加了击穿电压。

公开(公告)号：US20020134983A1

公开(公告)日：2002-09-26

申请号：US10079512

申请日：2002-02-22

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei Yamazaki

IPC分类号： G02F001/136 ,  H01L031/036 ,  H01L027/01 ,  H01L031/0392 ,  H01L031/20 ,  H01L031/0376 ,  H01L029/04 ,  G02F001/135 ,  H01L027/12

CPC分类号： H01L27/1214 ,  G02F1/13454 ,  H01L29/42384 ,  H01L2029/7863

摘要： In order to realize a higher reliability TFT and a high reliability semiconductor device, an NTFT of the present invention has a channel forming region, n-type first, second, and third impurity regions in a semiconductor layer. The second impurity region is a low concentration impurity region that overlaps a tapered potion of a gate electrode with a gate insulating film interposed therebetween, and the impurity concentration of the second impurity region increases gradually from the channel forming region to the first impurity region. And, the third impurity region is a low concentration impurity region that does not overlap the gate electrode. Moreover, a plurality of NTFTs on the same substrate should have different second impurity region lengths, respectively, according to difference of the operating voltages. That is, when the operating voltage of the second TFT is higher than the operating voltage of the first TFT, the length of the second impurity region is longer on the second TFT than on the first TFT.

摘要翻译： 为了实现更高可靠性的TFT和高可靠性半导体器件，本发明的NTFT在半导体层中具有沟道形成区域，n型第一，第二和第三杂质区域。 第二杂质区域是与栅电极的锥形部分重叠的低浓度杂质区域，其间插入有栅极绝缘膜，并且第二杂质区域的杂质浓度从沟道形成区域逐渐增加到第一杂质区域。 并且，第三杂质区域是不与栅电极重叠的低浓度杂质区域。 此外，根据工作电压的差异，同一基板上的多个NTFT分别具有不同的第二杂质区域长度。 也就是说，当第二TFT的工作电压高于第一TFT的工作电压时，第二TFT的第二杂质区域的长度比在第一TFT上长。

公开(公告)号：US20020121664A1

公开(公告)日：2002-09-05

申请号：US10074605

申请日：2002-02-12

申请人： Hanning Elektro-Werke GmbH & Co. KG

发明人： Dirk Priefert ,  Ralf Rudolf ,  Viktor Boguszewicz ,  Frank Michalzik ,  Rolf Buckhorst

IPC分类号： H01L031/0392 ,  H01L027/12 ,  H01L027/01

CPC分类号： H01L29/7393 ,  H01L27/1203 ,  H01L29/861

摘要： A lateral semiconductor element (10) in thin-film SOI technology comprises an insulator layer (14) which rests on a substrate (12) and is buried under a thin silicon film (16), on top of which the source, or anode, contact (18) and the drain, or cathode, contact (22b) are mounted. The anode contact (18) and the cathode contact (22) each lie over separate shield regions (28,30) within substrate (12), with the anode contact (18) being electrically connected with substrate (12).

摘要翻译： 薄膜SOI技术中的横向半导体元件（10）包括沉积在衬底（12）上并被埋在薄硅膜（16）下面的绝缘体层（14），其上的源极或阳极， 触点（18）和漏极（阴极）接触（22b）。 阳极接触件（18）和阴极接触件（22）各自位于衬底（12）内的分离的屏蔽区域（28,30）上，阳极接触件（18）与衬底（12）电连接。

公开(公告)号：US20020113265A1

公开(公告)日：2002-08-22

申请号：US10038084

申请日：2002-01-03

申请人： MEMC Electronic Materials, Inc.

发明人： Robert J. Falster

IPC分类号： H01L021/00 ,  H01L027/12 ,  H01L031/0392

CPC分类号： C30B15/203 ,  C30B15/206 ,  C30B29/06 ,  H01L21/3225 ,  H01L21/3226 ,  H01L21/7624 ,  H01L21/76251 ,  Y10S257/913 ,  Y10T428/21

摘要： The present invention relates to a silicon on insulator (nullSOInull) structure having a low defect density device layer and, optionally, a handle wafer having improved gettering capabilities. The device layer comprises a central axis, a circumferential edge, a radius extending from the central axis to the circumferential edge, and a first axially symmetric region which is substantially free of agglomerated intrinsic point defects. Additionally, the present invention is directed to such a SOI structure which has a Czochralski single crystal silicon handle wafer which is capable of forming an ideal, non-uniform depth distribution of oxygen precipitates upon being subjected to the heat treatment cycles of essentially any arbitrary electronic device manufacturing process.

摘要翻译： 本发明涉及具有低缺陷密度器件层的绝缘体上硅（SOI）结构，以及可选地具有改善的吸杂能力的处理晶片。 装置层包括中心轴线，圆周边缘，从中心轴线延伸到圆周边缘的半径以及基本上没有附聚本征点缺陷的第一轴对称区域。 另外，本发明涉及这样的SOI结构，其具有切克劳斯基单晶硅处理晶片，其能够在经受基本上任何任意电子的热处理循环后形成理想的，不均匀的氧沉淀物的深度分布 设备制造过程。

公开(公告)号：US20020105032A1

公开(公告)日：2002-08-08

申请号：US09872429

申请日：2001-06-01

申请人： Samsung Elecronics Co., Ltd.

发明人： Soo-Cheol Lee ,  Tae-Jung Lee

IPC分类号： H01L027/01 ,  H01L027/12 ,  H01L031/0392

CPC分类号： H01L29/66772 ,  H01L27/1203 ,  H01L29/78615 ,  H01L29/78621

摘要： A silicon-on-insulator (SOI) integrated circuit and a method of fabricating the SOI integrated circuit are provided. A plurality of transistor active regions and at least one body contact active region are formed on an SOI substrate. A semiconductor residue layer, which is thinner than the transistor active regions and the body contact active region, is disposed between the transistor active regions and the body contact active region. The transistor active regions, the body contact active region and the semiconductor residue layer are disposed on a buried insulating layer of the SOI substrate. The semiconductor residue layer is covered with a partial trench isolation layer. A bar-shaped full trench isolation layer is interposed between the adjacent transistor active regions. The full trench isolation layer is in contact with sidewalls of the transistor active regions adjacent thereto and is in contact with the buried insulating layer between the adjacent transistor active regions. An insulated gate pattern crosses over the respective transistor active regions. The insulated gate pattern is disposed to be parallel with the full trench isolation layer.

摘要翻译： 提供了绝缘体上硅（SOI）集成电路和制造SOI集成电路的方法。 在SOI衬底上形成多个晶体管有源区和至少一个体接触有源区。 比晶体管有源区域和体接触有源区域薄的半导体残留层设置在晶体管有源区域和体接触有源区域之间。 晶体管有源区，体接触有源区和半导体残留层设置在SOI衬底的掩埋绝缘层上。 半导体残渣层被部分沟槽隔离层覆盖。 在相邻的晶体管有源区域之间插入条形全沟槽隔离层。 全沟槽隔离层与与其相邻的晶体管有源区的侧壁接触并与相邻的晶体管有源区之间的掩埋绝缘层接触。 绝缘栅极图案跨过相应的晶体管有源区。 绝缘栅极图案设置成与全沟槽隔离层平行。

公开(公告)号：US20020100939A1

公开(公告)日：2002-08-01

申请号：US10090607

申请日：2002-03-06

申请人： MITSUBISHI DENKI KABUSHIKI KAISHA

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto

IPC分类号： H01L021/76 ,  H01L027/12

CPC分类号： H01L21/84 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76283 ,  H01L27/1203

摘要： In a combined isolation oxide film (BT1), a part closer to a gate electrode (GT13) reaches a buried oxide film (2) through an SOI layer (3) while a part closer to another gate electrode (GT12) has a sectional shape provided with a well region on its lower portion. The shape of an edge portion of the combined isolation oxide film (BT1) is in the form of a bird's beak in a LOCOS isolation oxide film. Consequently, the thicknesses of portions defining edge portions of the gate oxide films (GO12, GO13) are locally increased. Thus provided are a semiconductor device including a MOS transistor having a gate oxide film prevented from dielectric breakdown without increasing its thickness and a method of manufacturing the same.

摘要翻译： 在组合隔离氧化膜（BT1）中，靠近栅电极（GT13）的部分通过SOI层（3）到达埋入氧化膜（2），而靠近另一栅电极（GT12）的部分具有截面形状 在其下部设置有井区。 组合隔离氧化膜（BT1）的边缘部分的形状在LOCOS隔离氧化膜中呈鸟喙的形式。 因此，限定栅极氧化膜（GO12，GO13）的边缘部分的部分的厚度局部增加。 这样提供了一种半导体器件及其制造方法，该半导体器件包括具有防止绝缘击穿而不增加其厚度的栅极氧化膜的MOS晶体管。

公开(公告)号：US20020068388A1

公开(公告)日：2002-06-06

申请号：US10006043

申请日：2001-12-04

发明人： Satoshi Murakami ,  Yosuke Tsukamoto ,  Tomoaki Atsumi ,  Masayuki Sakakura

IPC分类号： H01L029/04 ,  H01L031/036 ,  H01L021/00 ,  H01L031/0376 ,  H01L031/20 ,  H01L021/84 ,  H01L027/01 ,  H01L027/12 ,  H01L031/0392

CPC分类号： H01L29/04 ,  G02F1/13454 ,  G02F1/136204 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124

摘要： In manufacturing a semiconductor device, static electricity is generated while contact holes are formed in an interlayer insulating film by dry etching. Damage to a pixel region or a driving circuit region due to travel of the static electricity generated is prevented. Gate signal lines are spaced apart from each other above a crystalline semiconductor film. Therefore a first protective circuit is not electrically connected when contact holes are opened in an interlayer insulating film. The static electricity generated during dry etching for opening the contact holes moves from the gate signal line, damages a gate insulating film, passes the crystalline semiconductor film, and again damages the gate insulating film before it reaches the gate signal line. As the static electricity generated during the dry etching damages the first protective circuit. the energy of the static electricity is reduced until it loses the capacity of damaging a driving circuit TFT. The driving circuit TFT is thus prevented from suffering electrostatic discharge damage.

摘要翻译： 在制造半导体器件时，通过干蚀刻在层间绝缘膜中形成接触孔时产生静电。 防止了由于所产生的静电的行进而对像素区域或驱动电路区域的损害。 栅极信号线在结晶半导体膜之上彼此间隔开。 因此，当在层间绝缘膜中打开接触孔时，第一保护电路不电连接。 在干蚀刻期间产生的用于打开接触孔的静电从栅极信号线移动，损坏栅极绝缘膜，通过晶体半导体膜，并且在栅极绝缘膜到达栅极信号线之前再次损坏栅极绝缘膜。 由于在干蚀刻期间产生的静电损伤第一保护电路。 静电的能量减少，直到损失驱动电路TFT的能力。 从而防止了驱动电路TFT遭受静电放电损坏。

公开(公告)号：US20020053706A1

公开(公告)日：2002-05-09

申请号：US09910304

申请日：2001-07-20

申请人： Samsung Electronics Co., Ltd.

发明人： Mu-kyeng Jung ,  Byung-sun Kim

IPC分类号： H01L027/01 ,  H01L029/76 ,  H01L029/94 ,  H01L027/12

CPC分类号： H01L27/1203 ,  H01L23/522 ,  H01L27/0207 ,  H01L29/7841 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a signal processing system having a metal oxide semiconductor (MOS) transistor with a silicon-on-insulator (SOI) structure are provided. The semiconductor device and the signal processing system include a main MOS transistor and an assistance MOS transistor. The main MOS transistor includes a first gate interconnection for receiving an external signal, first source/drain regions of a first conductivity type, and a body. The assistance MOS transistor includes a second gate interconnection and second source/drain regions of a second conductivity type opposite to the first conductivity type. The assistance MOS transistor selectively floats or grounds the body according to the external signal. The first gate interconnection and the second gate interconnection are electrically connected to each other by an interconnection layer.

摘要翻译： 提供了具有绝缘体上硅（SOI）结构的金属氧化物半导体（MOS）晶体管的半导体器件和信号处理系统。 半导体器件和信号处理系统包括主MOS晶体管和辅助MOS晶体管。 主MOS晶体管包括用于接收外部信号的第一栅极互连，第一导电类型的第一源极/漏极区域和主体。 辅助MOS晶体管包括与第一导电类型相反的第二导电类型的第二栅极互连和第二源/漏区。 辅助MOS晶体管根据外部信号有选择地漂浮或接地身体。 第一栅极互连和第二栅极互连通过互连层彼此电连接。

公开(公告)号：US20020037607A1

公开(公告)日：2002-03-28

申请号：US09860635

申请日：2001-05-21

发明人： Young-Hoon Kim

IPC分类号： H01L021/84 ,  H01L021/00 ,  H01L031/0392 ,  H01L027/01 ,  H01L027/12

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： The semiconductor substrate body-substrate contact structure for a SOI device includes an SOI substrate having a semiconductor substrate, a buried insulating film formed on an upper surface of the semiconductor substrate, and a semiconductor body layer formed on an upper surface of the buried insulating film. The SOI substrate includes a trench exposing an upper surface of the semiconductor substrate, and semiconductive side wall spacers are formed on side walls of the trench. A device isolation insulating film is formed in the trench.

摘要翻译： SOI器件的半导体衬底主体 - 衬底接触结构包括具有半导体衬底的SOI衬底，形成在半导体衬底的上表面上的埋入绝缘膜以及形成在埋入绝缘膜的上表面上的半导体本体层 。 SOI衬底包括暴露半导体衬底的上表面的沟槽，并且在沟槽的侧壁上形成半导体侧壁间隔物。 在沟槽中形成器件隔离绝缘膜。