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    SYSTEMS AND METHODS FOR ELECTROSTATIC TRAPPING OF CONTAMINANTS IN CRYOGENIC REFRIGERATION SYSTEMS
    141.
    发明申请
    SYSTEMS AND METHODS FOR ELECTROSTATIC TRAPPING OF CONTAMINANTS IN CRYOGENIC REFRIGERATION SYSTEMS 审中-公开

    公开(公告)号：US20170227267A1

    公开(公告)日：2017-08-10

    申请号：US15502165

    申请日：2015-08-05

    Applicant: D-Wave Systems Inc.

    Inventor： Sergey Uchaykin

    IPC: F25B43/00 ,  B03C3/45 ,  B03C3/41 ,  F25B9/14

    CPC classification number: F25B43/00 ,  B03C3/41 ,  B03C3/45 ,  B03C2201/06 ,  F25B9/145

    Abstract: Systems and methods for improving the performance of dilution refrigeration systems are described. Electrostatic cryogenic cold traps employed in the helium circuit of a dilution refrigerator improve the removal efficiency of contaminants from the helium circuit. An ionization source ionizes at least a portion of a refrigerant that includes helium and number of contaminants. The ionized refrigerant passes through an electrostatic cryogenic cold trap that includes a number of surfaces at one or more temperatures along at least a portion of the fluid passage between the cold trap inlet and the cold trap outlet. A high voltage source coupled to the surfaces to causes a first plurality of surfaces to function as electrodes at a first potential and a second plurality of surfaces to function as electrodes at a second potential. As ionized contaminants release their charge on the electrodes, the contaminants bond to the electrodes.

    Systems and methods for achieving orthogonal control of non-orthogonal qubit parameters
    142.
    发明授权
    Systems and methods for achieving orthogonal control of non-orthogonal qubit parameters 有权

    公开(公告)号：US09727823B2

    公开(公告)日：2017-08-08

    申请号：US14339289

    申请日：2014-07-23

    Applicant: D-WAVE SYSTEMS INC.

    Inventor： Mohammad H. S. Amin ,  Trevor Michael Lanting ,  Colin Enderud

    IPC: G06F15/00 ,  G06F15/18 ,  G06N99/00

    CPC classification number: G06N99/002

    Abstract: Achieving orthogonal control of non-orthogonal qubit parameters of a logical qubit allows for increasing the length of a qubit chain thereby increasing the effective connectivity of the qubit chain. A hybrid qubit is formed by communicatively coupling a dedicated second qubit to a first qubit. By tuning a programmable parameter of the second qubit of a hybrid qubit, an effective programmable parameter of the hybrid qubit is adjusted without affecting another effective programmable parameter of the hybrid qubit thereby achieving orthogonal control of otherwise non-orthogonal qubit parameters. The length of the logical qubit may thus be increased by communicatively coupling a plurality of such hybrid qubits together.

    SYSTEMS AND METHODS FOR IMPROVING THE PERFORMANCE OF A QUANTUM PROCESSOR TO REDUCE INTRINSIC/CONTROL ERRORS
    146.
    发明申请
    SYSTEMS AND METHODS FOR IMPROVING THE PERFORMANCE OF A QUANTUM PROCESSOR TO REDUCE INTRINSIC/CONTROL ERRORS 审中-公开
    改善量子处理器性能以减少内部/控制错误的系统和方法

    公开(公告)号：US20170017894A1

    公开(公告)日：2017-01-19

    申请号：US14829342

    申请日：2015-08-18

    Applicant: D-Wave Systems Inc.

    Inventor： Trevor Michael Lanting ,  Andrew King

    IPC: G06N99/00 ,  G06F15/82

    Abstract: Techniques for improving the performance of a quantum processor are described. Some techniques employ reducing intrinsic/control errors by using quantum processor-wide problems specifically crafted to reveal errors so that corrections may be applied. Corrections may be applied to physical qubits, logical qubits, and couplers so that problems may be solved using quantum processors with greater accuracy.

    Abstract translation: 描述了用于改善量子处理器的性能的技术。 一些技术通过使用专门制作的量子处理器范围的问题来减少内在/控制误差，以揭示错误，从而可以应用校正。 校正可以应用于物理量子位，逻辑量子位和耦合器，以便可以使用量子处理器更精确地解决问题。

    Systems and methods that formulate embeddings of problems for solving by a quantum processor
    147.
    发明授权
    Systems and methods that formulate embeddings of problems for solving by a quantum processor 有权
    制定和量化处理器解决问题嵌入的系统和方法

    公开(公告)号：US09501747B2

    公开(公告)日：2016-11-22

    申请号：US14109663

    申请日：2013-12-17

    Applicant: D-Wave Systems Inc.

    Inventor： Aidan Patrick Roy

    IPC: G06N99/00 ,  B82Y10/00

    CPC classification number: G06N99/002 ,  B82Y10/00 ,  G06N5/003 ,  G06N99/005

    Abstract: Systems and methods allow formulation of embeddings of problems via targeted hardware (e.g., particular quantum processor). In a first stage, sets of connected subgraphs are successively generated, each set including a respective subgraph for each decision variable in the problem graph, adjacent decisions variables in the problem graph mapped to respective vertices in the hardware graph, the respective vertices which are connected by at least one respective edge in the hardware graph. In a second stage, the connected subgraphs are refined such that no vertex represents more than a single decision variable.

    Abstract translation: 系统和方法允许通过目标硬件（例如特定的量子处理器）来制定问题的嵌入。 在第一阶段中，连续生成一组连接的子图，每个集合包括问题图中每个决策变量的相应子图，映射到硬件图中相应顶点的问题图中的相邻决策变量，连接的相应顶点 通过硬件图中的至少一个相应边缘。 在第二阶段，连接的子图被细化，使得没有顶点表示多于单个决策变量。

    SYSTEMS AND METHODS FOR QUANTUM PROCESSING OF DATA
    149.
    发明申请
    SYSTEMS AND METHODS FOR QUANTUM PROCESSING OF DATA 审中-公开

    公开(公告)号：US20160321559A1

    公开(公告)日：2016-11-03

    申请号：US14316366

    申请日：2014-06-26

    Applicant: D-Wave Systems Inc.

    Inventor： Geordie Rose ,  Suzanne Gildert ,  William G. Macready ,  Dominic Christoph Walliman

    IPC: G06N99/00

    CPC classification number: G06N99/005 ,  G06N99/002

    Abstract: Systems, methods and aspects, and embodiments thereof relate to unsupervised or semi-supervised features learning using a quantum processor. To achieve unsupervised or semi-supervised features learning, the quantum processor is programmed to achieve Hierarchal Deep Learning (referred to as HDL) over one or more data sets. Systems and methods search for, parse, and detect maximally repeating patterns in one or more data sets or across data or data sets. Embodiments and aspects regard using sparse coding to detect maximally repeating patterns in or across data. Examples of sparse coding include L0 and L1 sparse coding. Some implementations may involve appending, incorporating or attaching labels to dictionary elements, or constituent elements of one or more dictionaries. There may be a logical association between label and the element labeled such that the process of unsupervised or semi-supervised feature learning spans both the elements and the incorporated, attached or appended label.

    Systems and methods for solving computational problems
    150.
    发明授权
    Systems and methods for solving computational problems 有权
    用于解决计算问题的系统和方法

    公开(公告)号：US09405876B2

    公开(公告)日：2016-08-02

    申请号：US14186895

    申请日：2014-02-21

    Applicant: D-Wave Systems Inc.

    Inventor： William Macready ,  Geordie Rose ,  Thomas Mahon ,  Peter Love ,  Marshall Drew-Brook

    IPC: G06F17/50 ,  G06N99/00 ,  B82Y10/00

    CPC classification number: G06F17/505 ,  B82Y10/00 ,  G06F17/11 ,  G06N99/002

    Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.

    Abstract translation: 解决计算问题可能包括生成计算问题的逻辑电路表示，将逻辑电路表示编码为离散优化问题，以及使用量子处理器来解决离散优化问题。 可以钳位逻辑电路表示的输出，使得解决方案涉及有效地执行逻辑电路表示，以确定对应于被钳位的输出的输入。 该表示可以是布尔逻辑电路。 离散优化问题可以由一组微型优化问题组成，其中每个微型优化问题从逻辑电路表示编码相应的逻辑门。 量子处理器可以包括多组量子位，每组量子位耦合到相应的退火信号线，使得每组量子位的动态演化独立于其他量子位集合的动态演化被控制。

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