公开(公告)号：US11730066B2

公开(公告)日：2023-08-15

申请号：US17399375

申请日：2021-08-11

Applicant: D-WAVE SYSTEMS INC.

Inventor： Mark W. Johnson ,  Paul I. Bunyk ,  Andrew J. Berkley ,  Richard G. Harris ,  Kelly T. R. Boothby ,  Loren J. Swenson ,  Emile M. Hoskinson ,  Christopher B. Rich ,  Jan E. S. Johansson

IPC: H10N60/12 ,  G06N10/00 ,  H10N60/80

CPC classification number: H10N60/124 ,  G06N10/00 ,  H10N60/805

Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.

公开(公告)号：US20210190885A1

公开(公告)日：2021-06-24

申请号：US17054631

申请日：2019-05-16

Applicant: D-WAVE SYSTEMS INC.

Inventor： Loren J. Swenson ,  Emile M. Hoskinson ,  Mark H. Volkmann ,  Andrew J. Berkley ,  George E.G. Sterling ,  Jed D. Whittaker

IPC: G01R33/035 ,  H01L39/22 ,  G06N10/00

Abstract: Superconducting integrated circuits may advantageously employ superconducting resonators coupled to a microwave transmission line to efficiently address superconducting flux storage devices. In an XY-addressing scheme, a global flux bias may be applied to a number of superconducting flux storage devices via a low-frequency address line, and individual superconducting flux storage devices addressed via application of high-frequency pulses via resonators driven by the microwave transmission line. Frequency multiplexing can be employed to provide signals to two or more resonators. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to provide Z-addressing. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to eliminate a flux bias line. A low-frequency current bias may be used at room temperature to identify the presence of a DC short, an open, and/or an unexpected resistance in a superconducting resonator.

公开(公告)号：US11847534B2

公开(公告)日：2023-12-19

申请号：US17272052

申请日：2019-08-22

Applicant: D-WAVE SYSTEMS INC.

Inventor： Jed D. Whittaker ,  Loren J. Swenson ,  Ilya V. Perminov ,  Abraham J. Evert ,  Peter D. Spear ,  Mark H. Volkmann ,  Catia Baron Aznar ,  Michael S. Babcock

IPC: G06N10/00 ,  G01R33/035 ,  H03F19/00 ,  H10N69/00

CPC classification number: G06N10/00 ,  G01R33/0358 ,  H03F19/00 ,  H10N69/00

Abstract: A superconducting readout system employing a microwave transmission line, and a microwave superconducting resonator communicatively coupled to the microwave transmission line, and including a superconducting quantum interference device (SQUID), may be advantageously calibrated at least in part by measuring a resonant frequency of the microwave superconducting resonator in response to a flux bias applied to the SQUID, measuring a sensitivity of the resonant frequency in response to the flux bias, and selecting an operating frequency and a sensitivity of the microwave superconducting resonator based at least in part on a variation of the resonant frequency as a function of the flux bias. The flux bias may be applied to the SQUID by an interface inductively coupled to the SQUID. Calibration of the superconducting readout system may also include determining at least one of a propagation delay, a microwave transmission line delay, and a microwave transmission line phase offset.

公开(公告)号：US11839164B2

公开(公告)日：2023-12-05

申请号：US16996595

申请日：2020-08-18

Applicant: D-WAVE SYSTEMS INC.

Inventor： Loren J. Swenson ,  George E. G. Sterling ,  Christopher B. Rich

IPC: H10N60/12 ,  G11C11/44 ,  H03K3/38 ,  H03K17/92 ,  G11C8/00 ,  G06N10/40 ,  G11C8/10 ,  H10N60/80 ,  H10N69/00

CPC classification number: H10N60/12 ,  G06N10/40 ,  G11C8/00 ,  G11C8/10 ,  G11C11/44 ,  H03K3/38 ,  H03K17/92 ,  H10N60/805 ,  H10N69/00

Abstract: Addressing a superconducting flux storage device may include applying a bias current, a low-frequency flux bias, and a high-frequency flux bias in combination to cause a combined address signal level to exceed a defined address signal latching level for the superconducting flux storage device. A bias current that, in combination with a low-frequency flux bias and a high-frequency flux bias, causes a combined address signal level to exceed a defined address signal latching level for a superconducting flux storage device is at least reduced by an asymmetry in the Josephson junctions of the CJJ. A low-frequency flux bias that, in combination with a bias current and a high-frequency flux bias, causes a combined address signal level to exceed a defined address signal latching level for a superconducting flux storage device is at least reduced by an asymmetry in the Josephson junctions of the CJJ.

公开(公告)号：US11561269B2

公开(公告)日：2023-01-24

申请号：US17388545

申请日：2021-07-29

Applicant: D-WAVE SYSTEMS INC.

Inventor： Loren J. Swenson ,  Andrew J. Berkley ,  Mark H. Volkmann ,  George E. G. Sterling ,  Jed D. Whittaker

IPC: G01R33/035 ,  H01L39/22 ,  G06N10/00

Abstract: A device is dynamically isolated via a broadband switch that includes a plurality of cascade elements in series, wherein each cascade element comprises a first set of SQUIDs in series, a matching capacitor, and a second set of SQUIDs in series. The broadband switch is set to a passing state via flux bias lines during programming and readout of the device and set to a suppression state during device's calculation to reduce operation errors at the device. A device is electrically isolated from high-frequencies via an unbiased broadband switch. A device is coupled to a tunable thermal bath that includes a broadband switch.

公开(公告)号：US20220222558A1

公开(公告)日：2022-07-14

申请号：US17584600

申请日：2022-01-26

Applicant: D-WAVE SYSTEMS INC.

Inventor： Steven P. Reinhardt ,  Andrew D. King ,  Loren J. Swenson ,  Warren T.E. Wilkinson ,  Trevor Michael Lanting

IPC: G06N10/00 ,  G05B19/042

Abstract: Computational systems and methods employ characteristics of a quantum processor determined or sampled between a start and an end of an annealing evolution per an annealing schedule. The annealing evolution can be reinitialized, reversed or continued after determination. The annealing evolution can be interrupted. The annealing evolution can be ramped immediately prior to or as part of determining the characteristics. The annealing evolution can be paused or not paused immediately prior to ramping. A second representation of a problem can be generated based at least in part on the determined characteristics from an annealing evolution performed on a first representation of the problem. The determined characteristics can be autonomously compared to an expected behavior, and alerts optionally provided and/or the annealing evolution optionally terminated based on the comparison. Iterations of annealing evolutions may be performed until an exit condition occurs.

公开(公告)号：US20210384406A1

公开(公告)日：2021-12-09

申请号：US17321819

申请日：2021-05-17

Applicant: D-WAVE SYSTEMS INC.

Inventor： Shuiyuan Huang ,  Byong H. Oh ,  Douglas P. Stadtler ,  Edward G. Sterpka ,  Paul I. Bunyk ,  Jed D. Whittaker ,  Fabio Altomare ,  Richard G. Harris ,  Colin C. Enderud ,  Loren J. Swenson ,  Nicolas C. Ladizinsky ,  Jason J. Yao ,  Eric G. Ladizinsky

IPC: H01L39/24 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/18 ,  H01L39/12

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

公开(公告)号：US20210232364A1

公开(公告)日：2021-07-29

申请号：US17148850

申请日：2021-01-14

Applicant: D-WAVE SYSTEMS INC.

Inventor： Loren J. Swenson

IPC: G06F7/22 ,  G06N10/00 ,  H03H11/04 ,  H03H11/36

Abstract: A filter multiplexer for variable bandwidth annealing selection is described. The filter multiplexer has multiple pathways, where each pathway comprises a switch and a filter. Each filter has a different cutoff frequency from the other filters. Switches may be cryogenic switches. Each pathway may be communicatively coupled to an external annealing line. Upon receiving a problem, an annealing bandwidth can be selected, set or configured via the multiplexer to operate a quantum processor with a desired annealing schedule. The multiplexer may be used for calibration of a quantum processor by performing a calibration with a large annealing bandwidth, then calibrating the quantum processor by iterating through all available annealing bandwidths from the multiplexer.

公开(公告)号：US20210013391A1

公开(公告)日：2021-01-14

申请号：US16098801

申请日：2017-05-03

Applicant: D-WAVE SYSTEMS INC.

Inventor： Mark W. Johnson ,  Paul I. Bunyk ,  Andrew J. Berkley ,  Richard G. Harris ,  Kelly T. R. Boothby ,  Loren J. Swenson ,  Emile M. Hoskinson ,  Christopher B. Rich ,  Jan E.S. Johansson

IPC: H01L39/22 ,  G06N10/00 ,  H01L39/02

Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.

公开(公告)号：US20180218281A1

公开(公告)日：2018-08-02

申请号：US15881307

申请日：2018-01-26

Applicant: D-Wave Systems Inc.

Inventor： Steven P. Reinhardt ,  Andrew D. King ,  Loren J. Swenson ,  Warren T.E. Wilkinson ,  Trevor Michael Lanting

IPC: G06N99/00 ,  G05B19/042

CPC classification number: G06N10/00 ,  G05B19/042 ,  G05B2219/25071

Abstract: Computational systems and methods employ characteristics of a quantum processor determined or sampled between a start and an end of an annealing evolution per an annealing schedule. The annealing evolution can be reinitialized, reversed or continued after determination. The annealing evolution can be interrupted. The annealing evolution can be ramped immediately prior to or as part of determining the characteristics. The annealing evolution can be paused or not paused immediately prior to ramping. A second representation of a problem can be generated based at least in part on the determined characteristics from an annealing evolution performed on a first representation of the problem. The determined characteristics can be autonomously compared to an expected behavior, and alerts optionally provided and/or the annealing evolution optionally terminated based on the comparison. Iterations of annealing evolutions may be performed until an exit condition occurs.