公开(公告)号：US11468928B2

公开(公告)日：2022-10-11

申请号：US17222388

申请日：2021-04-05

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Kyung Suk Oh

IPC: G11C5/06 ,  G11C7/22 ,  G11C29/02 ,  G11C11/4063 ,  G11C5/04 ,  G11C11/4097 ,  G11C7/18 ,  G11C5/02

Abstract: A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A memory controller sends register values, for storage in a plurality of registers of a respective memory device. The register values include register values that represent one or more impedance values of on-die termination (ODT) impedances to apply to the respective inputs of the respective memory device that receive the CA signals, and one or more register values to selectively enable application of a chip select ODT impedance to the chip select input of the respective memory device.

公开(公告)号：US11450374B2

公开(公告)日：2022-09-20

申请号：US16953196

申请日：2020-11-19

Applicant: Rambus Inc.

Inventor： Jade M. Kizer ,  Sivakumar Doraiswamy ,  Benedict Lau

IPC: G11C7/00 ,  G11C11/4076 ,  G06F13/16 ,  G06F13/40 ,  G11C8/18 ,  G11C7/22 ,  G11C11/4063 ,  G11C11/4072 ,  G11C11/4096

Abstract: An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.

公开(公告)号：US20220291992A1

公开(公告)日：2022-09-15

申请号：US17721735

申请日：2022-04-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John E. Linstadt ,  Liji Gopalakrishnan

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory system employs an addressing scheme to logically divide rows of memory cells into separate contiguous regions, one for data storage and another for error detection and correction (EDC) codes corresponding to that data. Data and corresponding EDC codes are stored in the same row of the same bank. Accessing data and corresponding EDC code in the same row of the same bank advantageously saves power and avoids bank conflicts. The addressing scheme partitions the memory without requiring the requesting processor to have an understanding of the memory partition.

公开(公告)号：US20220291985A1

公开(公告)日：2022-09-15

申请号：US17728621

申请日：2022-04-25

Applicant: Rambus Inc.

Inventor： Yuanlong Wang ,  Frederick A. Ware

IPC: G06F11/07 ,  H03M13/09 ,  H03M13/29 ,  G06F3/06 ,  G06F11/10 ,  H03M13/00 ,  G06F13/42 ,  H04L1/00 ,  H04L1/08 ,  H04L1/18 ,  G06F11/14

Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

公开(公告)号：US20220284947A1

公开(公告)日：2022-09-08

申请号：US17702475

申请日：2022-03-23

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  James E. Harris

IPC: G11C11/4093 ,  G11C5/04 ,  G11C5/06 ,  G11C8/12 ,  G11C7/22

Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.

公开(公告)号：US20220283743A1

公开(公告)日：2022-09-08

申请号：US17637724

申请日：2020-08-25

Applicant: Rambus Inc.

Inventor： Torsten Partsch

IPC: G06F3/06

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) dynamic random access memory (DRAM) device is disclosed. The IC DRAM device includes memory core circuitry organized into bank groups of storage cells, each bank group accessible via a corresponding bank group address. A command/address (C/A) interface receives C/A information defining a joint command. The joint command includes information specifying a first memory access operation, a first bank group address associated with the first memory access operation, and a second memory access operation to be automatically directed to the first bank group address.

公开(公告)号：US20220283219A1

公开(公告)日：2022-09-08

申请号：US17702581

申请日：2022-03-23

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G01R31/28 ,  G01R31/317 ,  G11C29/02 ,  G11C29/12 ,  G11C29/16 ,  G11C29/50 ,  G01R31/26 ,  H03L7/00

Abstract: A semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The semiconductor IC device further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.

公开(公告)号：US20220262415A1

公开(公告)日：2022-08-18

申请号：US17668571

申请日：2022-02-10

Applicant: Rambus Inc.

Inventor： Sreeja MENON ,  Charles J. WILSON ,  Sudhir Kumar Katla SHETTY ,  Larry ARBUTHNOT ,  Nikhil Raghavendra RAO

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G11C29/42

Abstract: System connections map interface connections between the memory device and the memory controller. The memory controller is configured with information about these ‘mapped’ connections. The memory controller uses the mapping information to: correctly present commands and addresses to the memory device, perform CA training on mapped connections, generate read training data that accounts for mapped connections, correctly address mapped memory device pins for write training per pin adjustments, correctly calculate error detection coding, and correctly read vendor identification information.

公开(公告)号：US20220253378A1

公开(公告)日：2022-08-11

申请号：US17728791

申请日：2022-04-25

Applicant: Rambus Inc.

Inventor： Thomas J. Sheffler ,  Lawrence Lai ,  Liang Peng ,  Bohuslav Rychlik

IPC: G06F12/02 ,  G11C7/22 ,  G11C7/10 ,  G11C8/10

Abstract: A memory device having a DRAM core and a register stores first data in the register before receiving first and second memory access commands via a command interface and before receiving second data via a data interface. The memory device responds to the first memory access command by writing the first data from the register to the DRAM core and responds to the second memory access command by writing the second data from the data interface to the DRAM core.

公开(公告)号：US20220245073A1

公开(公告)日：2022-08-04

申请号：US17677714

申请日：2022-02-22

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  John Eric Linstadt ,  Catherine Chen

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/40

Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.