公开(公告)号：US10664735B2

公开(公告)日：2020-05-26

申请号：US16277698

申请日：2019-02-15

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Gwenael Maillet ,  Jean-Louis Labyre ,  Gilles Bas

IPC: G06K19/07 ,  G06K7/00 ,  G05B21/02

Abstract: A method of reducing noise generated by pulse width modulation (PWM) signals includes generating a PWM pulse train using a first set of parameter values and modifying the PWM pulse train during a near-field communication so that the PWM pulse train is generated using a second set of parameter values. Modifying the PWM pulse train includes reducing at least one parameter value of the first set of parameter values. The method further includes resuming generation of the PWM pulse train using the first set of parameter values after the near-field communication.

公开(公告)号：US10659020B2

公开(公告)日：2020-05-19

申请号：US16271077

申请日：2019-02-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Jean Nicolai ,  Albert Martinez

IPC: H03K21/00 ,  H03K3/84 ,  H03K21/02 ,  H03K23/00 ,  H03K5/06 ,  H03K19/003

Abstract: A circuit includes a random oscillation number generator (RONG) configured to generate first and second pulse signals at first and second RONG outputs. A first counter is coupled to the first RONG output and generates a first count at a first counter output. A second counter is coupled to the second RONG output and generates a second count at a second counter output. A selection circuit is coupled to the first and second counter outputs and to the first and second RONG outputs. A first pulse shaper is connected between the first RONG output and the first counter, and a second pulse shaper is connected between the second RONG output and the second counter.

公开(公告)号：US20200099717A1

公开(公告)日：2020-03-26

申请号：US16698519

申请日：2019-11-27

Applicant: STMicroelectronics (Rousset) SAS ,  Proton World International N.V.

Inventor： Thierry Huque ,  Olivier Van Nieuwenhuyze ,  Alexandre Charles

IPC: H04L29/06 ,  H04W4/80 ,  H04W12/12 ,  H04W12/06 ,  H04W12/08

Abstract: A method and associated circuits protect data stored in a secure data circuit of a telecommunication device equipped with a near-field communication (NFC) router, a microcontroller, and the secure data circuit. In the method, each message received with the NFC router is parsed to retrieve a communication pipe identifier and an instruction code. The communication pipe identifier and the instruction code are compared to corresponding information in a filter table. Instruction codes of particular messages that attempt to modify a communication pipe by reassigning one end of the communication pipe from the port of the NFC router to a different circuit are acted upon. These messages are blocked from reaching the secure data circuit when the instruction code is not authorized in the filter table, and these messages are permitted when the instruction code is authorized in the filter table.

公开(公告)号：US20200067503A1

公开(公告)日：2020-02-27

申请号：US16540954

申请日：2019-08-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe Bienvenu

IPC: H03K17/12 ,  H03K17/0812

Abstract: In one embodiment, a circuit includes a plurality of elementary transistors connected in parallel between a node of application of a first potential of a power supply voltage and a node for coupling a load. The plurality of transistors includes a first assembly of elementary transistors having their gates coupled to a control node by a first circuit and a second assembly of elementary transistors having their gates coupled to the control node by a second circuit. The second circuit has two states, where the first and second circuits are configured to supply a substantially identical control voltage to the gates of the first and second assemblies of elementary transistors when the second circuit is in one of the two states.

公开(公告)号：US10560089B2

公开(公告)日：2020-02-11

申请号：US16161531

申请日：2018-10-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas Borrel ,  Jimmy Fort ,  Francesco La Rosa

IPC: H03L5/02 ,  H03K17/20 ,  H03K17/22

Abstract: A power supply voltage is monitored by a monitoring circuit including a band gap voltage generator core including a first node and a second node. A control circuit connected to the first and second nodes is configured to deliver a control signal on a first output node having a first state when an increasing power supply voltage is below a first threshold and having a second state when increasing power supply voltage exceeds the first threshold. The first threshold is at least equal to the band gap voltage. An equalization circuit also connected to the first and second nodes with feedback to the band gap voltage generator core generates the bandgap voltage at a second output node. The control signal operates to control actuation of the equalization circuit.

公开(公告)号：US10552365B2

公开(公告)日：2020-02-04

申请号：US15902473

申请日：2018-02-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Chama Ameziane El Hassani

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/40 ,  H03K19/00 ,  G06F13/16

Abstract: In some embodiments, a buffer stage device includes a data input for receiving a data signal, a clock input for receiving a clock signal, a data output and a processor that is configured to deliver, to the data output, the data from the data signal in synchronism with clock cycles of the clock signal. The processor includes a first buffer module configured to deliver, to the data output, each datum in synchronism with a first edge of the clock signal and during a first half of a clock cycle, and a second buffer module configured to hold the datum at the data output during the second half of the clock cycle.

公开(公告)号：US20200035671A1

公开(公告)日：2020-01-30

申请号：US16518436

申请日：2019-07-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Fabrice Marinet

IPC: H01L27/02 ,  H01L23/525

Abstract: An integrated circuit includes a circuit module storing sensitive data. An electrically conductive body at a floating potential is located in the integrated circuit and holds an initial amount of electric charge. In response to an attack attempting to access the sensitive data, electric charge is collected on the electrically conductive body. A protection circuit is configured to ground an output of the circuit module, and thus preclude access to the sensitive data, in response to collected amount of electric charge on the electrically conductive body differing from the initial amount and exceeding a threshold.

公开(公告)号：US20200020650A1

公开(公告)日：2020-01-16

申请号：US16503876

申请日：2019-07-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Bruno Nicolas ,  Daniele Fronte

IPC: H01L23/00

Abstract: An electronic chip includes a first well having a first PN junction located therein, a second buried well located under and separated from the first well, and a first region forming a second PN junction with the second well. A detection circuit is coupled to the first well and configured to output a digital signal that has a first logic value when a potential difference within the first region is above a threshold and a second logic value when the potential difference within the first region is below the threshold.

公开(公告)号：US10536836B2

公开(公告)日：2020-01-14

申请号：US15994607

申请日：2018-05-31

Applicant: STMicroelectronics (Rousset) SAS ,  STMICROELECTRONICS GMBH

Inventor： Thierry Meziache ,  Pierre Rizzo ,  Alexandre Charles ,  Juergen Boehler

IPC: H04B7/00 ,  H04W4/80 ,  G06K7/00 ,  G06K7/10 ,  H04B5/00

Abstract: A device, including a main element (ME) and a set of at least two auxiliary elements (SEi), said main element including a master SWP interface (MINT), each auxiliary element including a slave SWP interface (SLINTi) connected to said master SWP interface of said NFC element through a controllably switchable SWP link (LK) and management means (PRM, CTLM, AMGi) configured to control said SWP link switching for selectively activating at once only one slave SWP interface on said SWP link.

公开(公告)号：US10530374B2

公开(公告)日：2020-01-07

申请号：US16289225

申请日：2019-02-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Bruno Gailhard

IPC: H03L7/10 ,  H03L7/14 ,  H03L7/089 ,  H03L7/099

Abstract: A method can be used for managing the operation of a phase-locked loop. The loop includes an oscillator voltage controlled by a control signal and a phase comparator receiving a reference signal and a feedback signal which arises from the output signal of the oscillator. The method includes a detection of a possible absence of transitions on the feedback signal for a first duration and, in response to such an absence, a forcing of the lowering of the voltage of the control signal at least until a reappearance of transitions on the feedback signal.