公开(公告)号：US20240186195A1

公开(公告)日：2024-06-06

申请号：US18529064

申请日：2023-12-05

Applicant: STMicroelectronics International N.V.

Inventor： Laurent HERARD ,  Olivier ZANELLATO ,  Patrick LAURENT

IPC: H01L23/10 ,  H01L21/48 ,  H01L21/52 ,  H01L23/00 ,  H01L23/053 ,  H01L23/498

CPC classification number: H01L23/10 ,  H01L21/4846 ,  H01L21/52 ,  H01L23/053 ,  H01L23/49816 ,  H01L24/97 ,  H01L2224/97

Abstract: An integrated circuit package includes a support substrate having a mounting face and a lateral wall having an inner face and an outer face. The inner face delimits with the mounting face a cavity. The outer face includes a step extending outwardly of the package. An electronic chip disposed in the cavity and electrically connected to electrically-conductive contact pads. A sealing structure is bonded by a glue to an upper face of the lateral wall to seal the cavity. The glue does not spill out over the outer face of the lateral wall. Electrically-conductive connection elements are located over a lower face of the support substrate and electrically cooperate with the contact pads through an interconnection network located in the support substrate.

公开(公告)号：US20240179036A1

公开(公告)日：2024-05-30

申请号：US18059103

申请日：2022-11-28

Applicant: STMicroelectronics International N.V.

Inventor： Iztok BRATUZ ,  Vinko KUNC ,  Maksimiljan STIGLIC

IPC: H04L25/49

CPC classification number: H04L25/4904

Abstract: Various embodiments of the present disclosure disclose decoding techniques for mitigating data corruption due to duty cycle distortion, jitter, and other distortions to a digital signal. Decoding processes, apparatuses, and systems are provided that utilize a decoding framework for improving the accuracy of output bit streams generated from digital signals. An example process receives data indicative of a digital signal, generates a signal measurement for the digital signal that includes signal length descriptive between a two rising edges of a digital signal or two falling edges of the demodulated digital signal, and generates at least one portion of an output bit stream for the digital signal based at least in part on the signal measurement.

公开(公告)号：US20240170960A1

公开(公告)日：2024-05-23

申请号：US18512292

申请日：2023-11-17

Applicant: STMicroelectronics International N.V.

Inventor： Francois TAILLIET

IPC: H02H9/04

CPC classification number: H02H9/046

Abstract: An ESD protection circuit includes a first voltage limiter having a first input terminal electrically coupled to each first signal pad of an integrated circuit by a first diode mounted in reverse bias during the integrated circuit operation. The first voltage limiter is mounted to be conductive between each first signal pad and ground during a positive ESD on the first signal pad. A second voltage limiter is electrically coupled and mounted to be conductive in the same direction as the first voltage limiter, between an external power supply pad and ground. An internal node outputs an internal power supply voltage to the domain, and is passed through by a current in response to a positive ESD on the power supply pad which is lower than the current passing through the first voltage limiter. A blocking diode is electrically connected between the first input terminal and the power supply pad.

公开(公告)号：US11989148B2

公开(公告)日：2024-05-21

申请号：US17548101

申请日：2021-12-10

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Rupesh Singh

IPC: G06F13/42 ,  G06F1/06 ,  G06F1/08 ,  H03K3/037

CPC classification number: G06F13/42 ,  G06F1/06 ,  G06F1/08 ,  H03K3/037

Abstract: An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem include a clock edge selector configured to determine a phase difference between the first clock signal and the second clock signal and to select, based on the phase difference, either a rising edge or a falling edge of the second clock signal to control output of data from the first subsystem to the second subsystem.

公开(公告)号：US11979167B2

公开(公告)日：2024-05-07

申请号：US17876263

申请日：2022-07-28

Applicant: STMicroelectronics International N.V.

Inventor： Sharad Gupta ,  Ankur Bal

IPC: H03M1/06

CPC classification number: H03M1/0665

Abstract: A data weighted averaging (DWA) data word in a standard or normal form unary code format is first converted to a thermometer control word in an alternative or spatial form unary code format. The thermometer control word is then converted from the alternative or spatial form unary code format to output a corresponding binary word.

公开(公告)号：US20240128971A1

公开(公告)日：2024-04-18

申请号：US18481907

申请日：2023-10-05

Applicant: STMicroelectronics International N.V.

Inventor： Sameer VASHISHTHA ,  Saiyid Mohammad Irshad RIZVI ,  Paras GARG

IPC: H03K17/56

CPC classification number: H03K17/56 ,  H03K2005/00078

Abstract: An integrated circuit includes a current mode transmitter having a first driver and a second driver. The first driver receives a single bit data stream. The second driver receives a delayed data stream corresponding to the single bit data stream delayed by a clock cycle. The current mode transmitter has a transition detector that generates a bulk modulation signal having a first value when the single bit data stream is the same as the delayed data stream and having a second value when the single bit data stream is different from the delayed data stream. The transition detector supplies the bulk modulation signal to the bulk terminals of driver switches of the first and second drivers.

公开(公告)号：US11921537B2

公开(公告)日：2024-03-05

申请号：US17821398

申请日：2022-08-22

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Jeet Narayan Tiwari

IPC: G06F1/08 ,  H03K3/037 ,  H03K5/26 ,  H03K19/20 ,  H03M7/16

CPC classification number: G06F1/08 ,  H03K3/037 ,  H03K5/26 ,  H03K19/20 ,  H03M7/16

Abstract: An integrated circuit includes a first circuit block operating with a first clock signal and a second circuit block operating with a second clock signal. The first circuit block includes a clock phase generator that receives the first clock signal and outputs a plurality of phase signals. The first circuit block includes a phase selector that receives the phase signals and the second clock signal and selects one of the phase signals based on the second clock signal. The first circuit block transmits data to the second circuit block based on the selected phase signal.

公开(公告)号：US11901919B2

公开(公告)日：2024-02-13

申请号：US17723225

申请日：2022-04-18

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Abhishek Jain ,  Sharad Gupta

IPC: H03M3/00

CPC classification number: H03M3/378 ,  H03M3/46 ,  H03M3/496

Abstract: An integrated circuit includes a continuous time delta sigma analog-to-digital converter (CTDS ADC) and a test circuit for testing the CTDS ADC. The test circuit converts multi-bit digital reference data to a single-bit digital stream. The test circuit then passes the single-bit digital stream to a finite impulse response digital-to-analog converter (FIR DAC). The FIR DAC converts the single-bit digital stream to an analog test signal. The analog test signal is then passed to the CTDS ADC. The CTDS ADC converts the analog test signal to digital test data. The test circuit analyzes the digital test data to determine the accuracy of the CTDS ADC.

公开(公告)号：US20240045458A1

公开(公告)日：2024-02-08

申请号：US18356818

申请日：2023-07-21

Applicant: STMicroelectronics International N.V.

Inventor： Zubair KHAN ,  Sandeep KAUSHIK

IPC: G05F1/575 ,  G05F1/46

CPC classification number: G05F1/575 ,  G05F1/468

Abstract: Provided are techniques for detecting a short circuit fault at an output of a regulator and protecting the regulator from the short circuit fault. An error amplifier receives a reference voltage and a feedback voltage and compares comparing the reference voltage with the feedback voltage for driving a power transistor of the regulator. A modification stage compares an output voltage of the voltage regulator with a fault reference voltage and in response to determining that the output voltage of the voltage regulator is less than the fault reference voltage, drives the power transistor using an internal node of the error amplifier by changing states of a first switch and a second switch and supplies the reference voltage to both the first and second inputs of the error amplifier by changing states of a third switch and a fourth switch.

公开(公告)号：US11892360B2

公开(公告)日：2024-02-06

申请号：US17136240

申请日：2020-12-29

Applicant: STMicroelectronics International N.V.

Inventor： Atul Dwivedi ,  Pijush Kanti Panja

IPC: G01K7/00 ,  H03K17/60

CPC classification number: G01K7/00 ,  H03K17/60 ,  G01K2219/00

Abstract: Circuitry generates base-to-emitter voltages (Vbe1, Vbe2) of two BJTs biased at different current densities, a base-to-emitter voltage (Vbe) of a BJT biased so Vbe is complementary to absolute temperature and has a curved non-linearity across temperature, and base-to-emitter voltages (Vbe1_c, Vbe2_c) of two BJTs biased by a temperature independent constant current and a current proportional to absolute temperature so Vbe2_c−Vbe1_c has the same but opposite curved non-linearity across temperature as Vbe. A sampling circuit samples these voltages and provides them to inputs of a loop filter. Filter outputs are quantized to produce a bitstream. The sampling circuit: when the received bit of the bitstream is zero, causes integration of Vbe1−Vbe2 to produce a voltage proportional to absolute temperature (αΔVbe); and when the received bit of the bitstream is one, causes integration of Vbe2_c−Vbe_Vbe1_c to produce a negative voltage complementary to absolute temperature −Vbe_c without non-linearity across temperature.