公开(公告)号：US09461134B1

公开(公告)日：2016-10-04

申请号：US14717553

申请日：2015-05-20

Applicant: ASM IP Holding B.V.

Inventor： Qi Xie ,  Fu Tang ,  Petri Raisanen ,  Jacob Woodruff ,  Jan Willem Maes ,  Michael Givens

IPC: H01L21/44 ,  H01L29/45 ,  H01L21/02 ,  H01L21/285 ,  H01L29/16 ,  H01L29/08 ,  H01L29/66 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L29/45 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/285 ,  H01L21/76831 ,  H01L23/291 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/0895 ,  H01L29/16 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/78

Abstract: In some embodiments, an MIS-type contact structure is formed by passivating the semiconductor surface of a source/drain region with a chalcogen, and subsequently depositing an tunnel layer by first exposing the chalcogen-passivated surface to a metal-organic precursor. Subsequently, deposition of the tunnel layer continues to a desired thickness. Preferably, the metal-organic precursor is part of a first set of ALD precursors and a second set of ALD precursors, which include one or more metal or semimetal precursors, are subsequently used to continue the deposition. For example, the metal-organic precursor may be used to deposit a first portion of the tunnel layer, and an inorganic metal or inorganic semimetal precursor or a different organic metal or organic semimetal precursor may be used to deposit a second portion of the tunnel layer. A metal is subsequently deposited on the tunnel layer, e.g., to form a metal electrode or electrical contact.

Abstract translation: 在一些实施例中，通过用硫族元素钝化源极/漏极区域的半导体表面并随后通过首先将硫属软化钝化表面暴露于金属 - 有机前体而沉积隧道层来形成MIS型接触结构。 随后，隧道层的沉积继续到期望的厚度。 优选地，金属 - 有机前体是第一组ALD前体的一部分，并且随后使用包括一种或多种金属或半金属前体的第二组ALD前体来继续沉积。 例如，金属有机前体可以用于沉积隧道层的第一部分，并且可以使用无机金属或无机半金属前体或不同的有机金属或有机半金属前体来沉积隧道层的第二部分 。 随后在隧道层上沉积金属，例如形成金属电极或电接触。

公开(公告)号：US20160203974A1

公开(公告)日：2016-07-14

申请号：US14992942

申请日：2016-01-11

Applicant: ASM IP Holding B.V.

Inventor： Suvi P. Haukka ,  Fu Tang ,  Michael E. Givens ,  Jan Willem Maes ,  Qi Xie

IPC: H01L21/02

CPC classification number: H01L21/02175 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/02334 ,  H01L21/0237 ,  H01L21/02395 ,  H01L21/02557 ,  H01L21/02568 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/28264 ,  H01L29/2203 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/7786 ,  H01L29/78

Abstract: In some aspects, methods of forming a metal sulfide thin film are provided. According to some methods, a metal sulfide thin film is deposited on a substrate in a reaction space in a cyclical process where at least one cycle includes alternately and sequentially contacting the substrate with a first vapor-phase metal reactant and a second vapor-phase sulfur reactant. In some aspects, methods of forming a three-dimensional architecture on a substrate surface are provided. In some embodiments, the method includes forming a metal sulfide thin film on the substrate surface and forming a capping layer over the metal sulfide thin film. The substrate surface may comprise a high-mobility channel.

公开(公告)号：US09385164B2

公开(公告)日：2016-07-05

申请号：US14256728

申请日：2014-04-18

Applicant: ASM IP Holding B.V.

Inventor： Qi Xie ,  Vladimir Machkaoutsan ,  Jan Willem Maes ,  Michael Givens ,  Petri Raisanen

IPC: H01L21/8242 ,  H01L27/24 ,  H01L45/00 ,  G11C13/00

CPC classification number: H01L27/2481 ,  G11C13/0007 ,  G11C2213/71 ,  H01L45/08 ,  H01L45/085 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1641

Abstract: A method for forming a resistive random access memory (RRAM) device is disclosed. The method comprises forming a first electrode, forming a resistive switching oxide layer comprising a metal oxide by thermal atomic layer deposition (ALD), doping the resistive switching oxide layer with a metal dopant different from metal forming the metal oxide, and forming a second electrode by thermal atomic layer deposition (ALD), where the resistive switching layer is interposed between the first electrode and the second electrode. In some embodiments, forming the resistive switching oxide may be performed without exposing a surface of the switching oxide layer to a surface-modifying plasma treatment after depositing the metal oxide.

Abstract translation: 公开了一种形成电阻随机存取存储器（RRAM）装置的方法。 该方法包括：形成第一电极，通过热原子层沉积（ALD）形成包含金属氧化物的电阻式开关氧化物层，用与形成金属氧化物的金属不同的金属掺杂剂掺杂电阻式开关氧化物层，以及形成第二电极 通过热原子层沉积（ALD），其中电阻式开关层介于第一电极和第二电极之间。 在一些实施例中，在沉积金属氧化物之后，可以进行形成电阻式开关氧化物而不使开关氧化物层的表面暴露于表面改性等离子体处理。

公开(公告)号：US20160097121A1

公开(公告)日：2016-04-07

申请号：US14966335

申请日：2015-12-11

Applicant: ASM IP HOLDING B.V.

Inventor： Christophe Pomarede ,  Eric Shero ,  Mohith Verghese ,  Jan Willem Maes ,  Chang-Gong Wang

IPC: C23C16/455 ,  H01L21/02 ,  H01L27/108

CPC classification number: C23C16/45525 ,  C23C14/246 ,  C23C16/045 ,  C23C16/448 ,  C23C16/4482 ,  C23C16/4485 ,  C23C16/4486 ,  C23C16/45527 ,  C23C16/45561 ,  C23C16/52 ,  F17C2205/0142 ,  F17C2205/0146 ,  F17C2270/0518 ,  H01J37/32449 ,  H01L21/02148 ,  H01L21/02172 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/3142 ,  H01L21/31645 ,  H01L27/10861

Abstract: A vapor deposition method and apparatus including at least two vessels containing a same first source chemical. A controller is programmed to simultaneously pulse to the reaction space doses or pulses of a gas from the vessels, each of the doses having a substantially consistent concentration of the first source chemical. The apparatus may also include at least two vessels containing a same second source chemical. The controller can be programmed to simultaneously pulse to the reaction space doses or pulses of a gas from the vessels containing the second source chemical, each of the doses having a substantially consistent concentration of the second source chemical. The second source chemical can be pulsed to the reaction space after the reaction space is purged of an excess of the first source chemical.

公开(公告)号：US09240412B2

公开(公告)日：2016-01-19

申请号：US14040196

申请日：2013-09-27

Applicant: ASM IP Holding B.V.

Inventor： Qi Xie ,  Vladimir Machkaoutsan ,  Jan Willem Maes

IPC: H01L21/336 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L27/0928 ,  H01L29/0649 ,  H01L29/165

Abstract: Semiconductor structures, devices, and methods of forming the structures and device are disclosed. Exemplary structures include multi-gate or FinFET structures that can include both re-channel MOS (NMOS) and p-channel MOS (PMOS) devices to form CMOS structures and devices on a substrate. The devices can be formed using selective epitaxy and shallow trench isolation techniques.

Abstract translation: 公开了形成结构和装置的半导体结构，器件和方法。 示例性结构包括可以包括再通道MOS（NMOS）和p沟道MOS（PMOS）器件的多栅极或FinFET结构，以在衬底上形成CMOS结构和器件。 可以使用选择性外延和浅沟槽隔离技术来形成器件。