公开(公告)号：US09324713B1

公开(公告)日：2016-04-26

申请号：US14658279

申请日：2015-03-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Bingwu Liu ,  Hui Zang ,  Lun Zhao

IPC: H01L21/8238 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/3083 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Method for forming FinFET source/drain regions with reduced field oxide loss and the resulting devices are disclosed. Embodiments include forming silicon fins separated by a field oxide on a silicon substrate; recessing the field oxide to reveal an upper portion of the silicon fins; forming a spacer layer conformally over the upper portion of the fins and over the field oxide; filling spaces between the fins with a material having high selectivity with the spacer layer; recessing the material; removing the spacer layer above an upper surface of the material; removing the material; recessing the upper portion of the fins; and epitaxially growing source/drain regions on the recessed fins.

Abstract translation: 公开了用于形成具有减小的场氧化物损耗的FinFET源极/漏极区域的方法以及所得到的器件。 实施例包括在硅衬底上形成由场氧化物分离的硅散热片; 凹陷场氧化物以露出硅散热片的上部; 在翅片的上部和场氧化物上方形成间隔层; 用具有间隔层的高选择性的材料填充翅片之间的空间; 凹陷材料; 在所述材料的上表面上方移除所述间隔层; 去除材料; 使翅片的上部凹陷; 并且在凹陷散热片上外延生长源极/漏极区域。

公开(公告)号：US09252273B2

公开(公告)日：2016-02-02

申请号：US14147181

申请日：2014-01-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L21/283 ,  H01L21/02 ,  H01L29/417 ,  H01L29/423 ,  H01L21/8234

CPC classification number: H01L29/7851 ,  H01L21/02057 ,  H01L21/02112 ,  H01L21/283 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823418 ,  H01L29/0653 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A process for fabrication of semiconductor devices, particularly fin-shaped Field Effect Transistors (FinFETs), having a low contact horizontal resistance and a resulting device are provided. Embodiments include: providing a substrate having source and drain regions separated by a gate region; forming a gate electrode having a first length on the gate region; forming an epitaxy layer on the source and drain regions; forming a contact layer having a second length, longer than the first length, at least partially on the epitaxy layer; and forming an oxide layer on top and side surfaces of the contact layer for at least the first length.

Abstract translation: 提供了具有低接触水平电阻的半导体器件，特别是鳍状场效应晶体管（FinFET）的制造方法以及所得到的器件。 实施例包括：提供具有由栅极区域分隔的源极和漏极区域的衬底; 在所述栅极区上形成具有第一长度的栅电极; 在源极和漏极区上形成外延层; 在所述外延层上至少部分地形成具有比所述第一长度长的第二长度的接触层; 以及在所述接触层的顶表面和侧表面上形成至少第一长度的氧化物层。

公开(公告)号：US09252203B2

公开(公告)日：2016-02-02

申请号：US14271515

申请日：2014-05-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bingwu Liu

IPC: H01L21/02 ,  H01L49/02 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide improved metal-insulator-metal (MIM) capacitors. In embodiments, series resistance is reduced by forming a via underneath the bottom plate of a MIM capacitor, leading to a metallization layer or intermediate metal sublayer. In embodiments, the MIM capacitor is formed with a corrugated shape to increase the plate surface area, allowing a thicker dielectric to be used, thereby mitigating leakage issues.

Abstract translation: 本发明的实施例提供改进的金属 - 绝缘体 - 金属（MIM）电容器。 在实施例中，通过在MIM电容器的底板下面形成通孔，导致金属化层或中间金属子层来减小串联电阻。 在实施例中，MIM电容器形成为波纹形状以增加板表面积，允许使用更厚的电介质，从而减轻漏电问题。

公开(公告)号：US09202894B1

公开(公告)日：2015-12-01

申请号：US14286144

申请日：2014-05-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang

IPC: H01L29/66 ,  H01L29/423

CPC classification number: H01L29/66795 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/78696

Abstract: One method includes forming trenches that define a fin structure including a first layer of a first semiconductor material and a second layer of a second semiconductor material positioned above a substrate, performing at least one etching process that exposes opposing end surfaces of the first and second layers, performing at least one recess etching process that removes end portions of the first layer and defines a cavity on opposite ends of the first layer, performing an epitaxial deposition process that fills each of the cavities with a support structure including a third semiconductor material, and performing an etching process to selectively remove remaining portions of the recessed first layer relative to the second layer and the support structures, the end portions of the second layer and the support structures defining pillars on opposite ends of the fin structure.

Abstract translation: 一种方法包括形成限定翅片结构的沟槽，所述鳍结构包括位于衬底上方的第一半导体材料的第一层和第二半导体材料的第二层，执行暴露第一和第二层的相对端面的至少一个蚀刻工艺 执行去除第一层的端部并限定第一层的相对端上的空腔的至少一个凹陷蚀刻工艺，执行利用包括第三半导体材料的支撑结构填充每个空腔的外延沉积工艺，以及 执行蚀刻工艺以相对于第二层和支撑结构选择性地去除凹陷的第一层的剩余部分，第二层的端部和支撑结构在翅片结构的相对端上限定支柱。

公开(公告)号：US20150325635A1

公开(公告)日：2015-11-12

申请号：US14271515

申请日：2014-05-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bingwu Liu

IPC: H01L49/02 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide improved metal-insulator-metal (MIM) capacitors. In embodiments, series resistance is reduced by forming a via underneath the bottom plate of a MIM capacitor, leading to a metallization layer or intermediate metal sublayer. In embodiments, the MIM capacitor is formed with a corrugated shape to increase the plate surface area, allowing a thicker dielectric to be used, thereby mitigating leakage issues.

Abstract translation: 本发明的实施例提供改进的金属 - 绝缘体 - 金属（MIM）电容器。 在实施例中，通过在MIM电容器的底板下面形成通孔，导致金属化层或中间金属子层来减小串联电阻。 在实施例中，MIM电容器形成为波纹形状以增加板表面积，允许使用更厚的电介质，从而减轻漏电问题。

公开(公告)号：US09129986B2

公开(公告)日：2015-09-08

申请号：US13929923

申请日：2013-06-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Hyun-Jin Cho

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/0653 ,  H01L29/1079 ,  H01L29/42372 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

Abstract: Approaches for spacer chamfering in a replacement metal gate (RMG) device are provided. Specifically, a semiconductor device is provided with a set of fins formed from a substrate; a silicon-based layer conformally deposited over the set of fins; an etch-stop layer (e.g., titanium nitride (TiN)) formed over the silicon-based layer, the etch-stop layer being selective to at least one of: silicon, oxide, and nitride; a set of RMG structures formed over the substrate; a set of spacers formed along each of the set of RMG structures, wherein a vertical layer of material from each of the set of spacers is removed selective to the etch-stop layer. By chamfering each sidewall spacer, a wider area for subsequent work-function (WF) metal deposition is provided. Meanwhile, each transistor channel region is covered by the etch-stop layer (e.g., TiN), which maintains the original gate critical dimension during reactive ion etching.

Abstract translation: 提供了替代金属门（RMG）设备中间隔倒角的方法。 具体地，半导体器件设置有由基板形成的一组翅片; 保形地沉积在该组翅片上的硅基层; 形成在硅基层上的蚀刻停止层（例如，氮化钛（TiN）），该蚀刻停止层对于硅，氧化物和氮化物中的至少一个是选择性的; 一组形成在衬底上的RMG结构; 沿着RMG结构集合中的每一个形成的一组隔离物，其中来自该组间隔物中的每一个的垂直材料层被选择性地移除到蚀刻停止层。 通过倒角每个侧壁间隔件，提供了用于后续功函（WF）金属沉积的较宽区域。 同时，每个晶体管沟道区域被蚀刻停止层（例如，TiN）覆盖，其在反应离子蚀刻期间维持原始栅极临界尺寸。

公开(公告)号：US09112032B1

公开(公告)日：2015-08-18

申请号：US14305457

申请日：2014-06-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bingwu Liu ,  Hui Zang

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L21/84 ,  H01L29/423

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66818

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin protection layer around a fin, forming a sacrificial gate electrode above a section of the fin protection layer, forming at least one sidewall spacer adjacent the sacrificial gate electrode, removing the sacrificial gate electrode to define a gate cavity that exposes a portion of the fin protection layer, oxidizing at least the exposed portion of the fin protection layer to thereby form an oxidized portion of the fin protection layer, and removing the oxidized portion of the fin protection layer so as to thereby expose a surface of the fin within the gate cavity.

Abstract translation: 本文公开的一种说明性方法包括在鳍周围形成翅片保护层，在翅片保护层的一部分上形成牺牲栅电极，形成邻近牺牲栅电极的至少一个侧壁间隔物，去除牺牲栅极 电极，以限定露出所述鳍片保护层的一部分的栅极腔，至少氧化所述鳍片保护层的暴露部分，从而形成所述鳍片保护层的氧化部分，以及去除所述鳍片保护层的氧化部分，从而 从而使得在门腔内的翅片的表面露出。

公开(公告)号：US11569356B2

公开(公告)日：2023-01-31

申请号：US17097419

申请日：2020-11-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Ruilong Xie ,  Jae Gon Lee

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L29/08 ,  H01L29/51 ,  H01L23/528 ,  H01L23/522

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a scaled gate contact and source/drain cap and methods of manufacture. The structure includes: a gate structure comprising an active region; source and drain contacts adjacent to the gate structure; a capping material over the source and drain contacts; a gate contact formed directly above the active region of the gate structure and over the capping material; a U-shape dielectric material around the gate contact, above the source and drain contacts; and a contact in direct electrical contact to the source and drain contacts.

公开(公告)号：US10811319B2

公开(公告)日：2020-10-20

申请号：US16204482

申请日：2018-11-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/417 ,  H01L21/311 ,  H01L27/088 ,  H01L21/321 ,  H01L29/165 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/027

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures; source and drain regions adjacent to respective gate structures of the plurality of gate structures; metallization features contacting selected source and drain regions; and recessed metallization features contacting other selected source and drain regions.

公开(公告)号：US10741451B2

公开(公告)日：2020-08-11

申请号：US16150651

申请日：2018-10-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Laertis Economikos ,  Shesh Mani Pandey ,  Chanro Park ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/762 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

Abstract: Processes form integrated circuit apparatuses that include parallel fins, wherein the fins are patterned in a first direction. Parallel gate structures intersect the fins in a second direction perpendicular to the first direction, wherein the gate structures have a lower portion adjacent to the fins and an upper portion distal to the fins. Source/drain structures are positioned on the fins between the gate structures. Source/drain contacts are positioned on the source/drain structures and multiple insulator layers are positioned between the gate structures and the source/drain contacts. Additional upper sidewall spacers are positioned between the upper portion of the gate structures and the multiple insulator layers.