公开(公告)号：US09054044B2

公开(公告)日：2015-06-09

申请号：US13788719

申请日：2013-03-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L29/06 ,  H01L21/308 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/3083 ,  H01L29/0657 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

Abstract: Semiconductor device structures and methods for forming a semiconductor device are provided. In embodiments, one or more fins are provided, each of the one or more fins having a lower portion and an upper portion disposed on the lower portion. The lower portion is embedded in a first insulating material. The shape of the upper portion is at least one of a substantially triangular shape and a substantially rounded shape and a substantially trapezoidal shape. Furthermore, a layer of a second insulating material different from the first insulating material is formed on the upper portion.

Abstract translation: 提供了用于形成半导体器件的半导体器件结构和方法。 在实施例中，提供一个或多个翅片，所述一个或多个翅片中的每一个具有设置在下部的下部和上部。 下部嵌入第一绝缘材料中。 上部的形状是基本上三角形形状和大致圆形形状和大致梯形形状中的至少一个。 此外，在上部形成有与第一绝缘材料不同的第二绝缘材料层。

公开(公告)号：US20150097252A1

公开(公告)日：2015-04-09

申请号：US14047517

申请日：2013-10-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Roman Boschke

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L21/76805 ,  H01L21/823828 ,  H01L21/823835 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7833

Abstract: When forming field effect transistors according to the gate-first HKMG approach, the cap layer formed on top of the gate electrode had to be removed before the silicidation step, resulting in formation of a metal silicide layer on the surface of the gate electrode and of the source and drain regions of the transistor. The present disclosure improves the manufacturing flow by skipping the gate cap removal process. Metal silicide is only formed on the source and drain regions. The gate electrode is then contacted by forming an aperture through the gate material, leaving the surface of the gate metal layer exposed.

Abstract translation: 当根据栅极第一HKMG方法形成场效应晶体管时，形成在栅电极顶部上的覆盖层必须在硅化步骤之前去除，导致在栅电极的表面上形成金属硅化物层，并且 晶体管的源极和漏极区域。 本公开通过跳过栅极盖去除工艺来改善制造流程。 仅在源区和漏区形成金属硅化物。 然后通过形成通过栅极材料的孔而使栅电极接触，留下栅极金属层的表面。

公开(公告)号：US20150041910A1

公开(公告)日：2015-02-12

申请号：US13961554

申请日：2013-08-07

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Stefan Flachowksy ,  Juergen Faul ,  Jan Hoentschel

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823807

Abstract: Integrated circuits and methods of fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a bulk silicon substrate that is lightly-doped with a first dopant type divided into a first device region and a second device region, and a well region that is lightly-doped with a second dopant type formed in the second device region. The integrate circuit further includes heavily-doped source/drain extension regions of the first dopant type aligned to a first gate electrode structure and heavily-doped source/drain extension regions of the second dopant type aligned to a second gate electrode structure, and an intermediately-doped halo region of the second dopant type formed underneath the first gate electrode structure and an intermediately-doped halo regions of the first dopant type underneath the second gate electrode structure. Still further, the integrated circuit includes heavily-doped source/drain regions.

Abstract translation: 提供集成电路和制造集成电路的方法。 在示例性实施例中，集成电路包括轻掺杂有分为第一器件区域和第二器件区域的第一掺杂剂类型的体硅衬底，以及形成第二掺杂剂类型的轻掺杂阱区 在第二设备区域中。 集成电路还包括与第一栅极电极结构对准的第一掺杂剂类型的重掺杂源极/漏极延伸区域和与第二栅电极结构对准的第二掺杂剂类型的重掺杂源极/漏极延伸区域，并且中间地 形成在第一栅电极结构下方的第二掺杂剂类型的掺杂晕圈区域和位于第二栅电极结构下方的第一掺杂剂类型的中间掺杂卤区。 此外，集成电路包括重掺杂源极/漏极区域。

公开(公告)号：US20150014777A1

公开(公告)日：2015-01-15

申请号：US13942034

申请日：2013-07-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Joerg Schoenekess ,  Jan Hoentschel

IPC: H01L27/088 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L29/66477

Abstract: The present disclosure provides an improved method for forming a thin semiconductor alloy layer on top of a semiconductor layer. The proposed method relies on an implantation of appropriate impurity species before performing deposition of the semiconductor alloy film. The implanted species cause the semiconductor alloy layer to be less unstable to wet and dry etches performed on the device surface after deposition. Thus, the thickness uniformity of the semiconductor alloy film may be substantially increased if the film is deposited after performing the implantation. On the other hand, some implanted impurities have been found to decrease the growth rate of the semiconductor alloy layer. Thus, by selectively implanting appropriate impurities in predetermined portions of a wafer, a single deposition step may be used in order to form a semiconductor alloy layer with a thickness which may be locally adjusted at will.

Abstract translation: 本公开提供了一种用于在半导体层的顶部上形成薄半导体合金层的改进方法。 所提出的方法依赖于在进行半导体合金膜的沉积之前植入适当的杂质物质。 植入的物质导致半导体合金层在沉积后在器件表面上进行的湿法干蚀刻不太稳定。 因此，如果在进行植入之后沉积膜，则半导体合金膜的厚度均匀性可以显着增加。 另一方面，已经发现一些植入的杂质降低了半导体合金层的生长速率。 因此，通过在晶片的预定部分选择性地注入合适的杂质，可以使用单个沉积步骤以形成可以随意地局部调整的厚度的半导体合金层。

公开(公告)号：US20140273375A1

公开(公告)日：2014-09-18

申请号：US13842077

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Peter Javorka ,  Ralf Richter ,  Jan Hoentschel

IPC: H01L21/266 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/823418 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656

Abstract: Methods for fabricating an integrated circuit are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming a gate electrode structure overlying a semiconductor substrate. A first sacrificial oxide layer is formed overlying the semiconductor substrate and a first implant mask is patterned overlying the first sacrificial oxide layer to expose a portion of the first sacrificial oxide layer adjacent the gate electrode structure. Conductivity determining ions are implanted into the semiconductor substrate, through the first sacrificial oxide layer. The first implant mask and the first sacrificial oxide layer are removed after implanting the conductivity determining ions into the semiconductor substrate.

Abstract translation: 本文提供了制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括形成覆盖半导体衬底的栅电极结构。 第一牺牲氧化物层被形成在半导体衬底上，并且第一注入掩模被图案化成覆盖在第一牺牲氧化物层上以暴露与栅电极结构相邻的第一牺牲氧化物层的一部分。 电导率确定离子通过第一牺牲氧化物层注入到半导体衬底中。 在将导电性确定离子注入半导体衬底之后，去除第一注入掩模和第一牺牲氧化物层。

公开(公告)号：US20140264626A1

公开(公告)日：2014-09-18

申请号：US14174474

申请日：2014-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Alban Zaka ,  Nicolas Sassiat ,  Jan Hoentschel ,  Martin Trentzsch ,  Carsten Grass

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/7833

Abstract: The present disclosure provides, in some aspects, a gate electrode structure for a semiconductor device. In some illustrative embodiments herein, the gate electrode structure includes a first high-k dielectric layer over a first active region of a semiconductor substrate and a second high-k dielectric layer on the first high-k dielectric layer. The first high-k dielectric layer has a metal species incorporated therein for adjusting the work function of the first high-k dielectric layer.

Abstract translation: 在一些方面，本公开提供了一种用于半导体器件的栅电极结构。 在本文的一些说明性实施例中，栅电极结构包括在半导体衬底的第一有源区上的第一高k电介质层和第一高k电介质层上的第二高k电介质层。 第一高k电介质层具有并入其中的金属物质，用于调节第一高k电介质层的功函数。

公开(公告)号：US20140256097A1

公开(公告)日：2014-09-11

申请号：US13785557

申请日：2013-03-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ran Yan ,  Nicolas Sassiat ,  Jan Hoentschel ,  Torben Balzer

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for forming a semiconductor device is provided which includes providing a gate structure in an active region of a semiconductor substrate, wherein the gate structure includes a gate insulating layer having a high-k material, a gate metal layer and a gate electrode layer, forming sidewall spacers adjacent to the gate structure and, thereafter, performing a fluorine implantation process. Also a method for forming a CMOS integrated circuit structure is provided which includes providing a semiconductor substrate with a first active region and a second active region, forming a first gate structure in the first active region and a second gate structure in the second active region, wherein each gate structure includes a gate insulating layer having a high-k material, a gate metal layer and a gate electrode layer, forming sidewall spacers adjacent to each of the first and second gate structures and, thereafter, performing a fluorine implantation process.

Abstract translation: 提供了一种用于形成半导体器件的方法，其包括在半导体衬底的有源区域中提供栅极结构，其中所述栅极结构包括具有高k材料，栅极金属层和栅极电极层的栅极绝缘层， 形成与栅极结构相邻的侧壁间隔，之后进行氟注入工艺。 还提供了一种用于形成CMOS集成电路结构的方法，其包括提供具有第一有源区和第二有源区的半导体衬底，在第一有源区中形成第一栅极结构，在第二有源区中形成第二栅极结构， 其中每个栅极结构包括具有高k材料，栅极金属层和栅极电极层的栅极绝缘层，形成与第一和第二栅极结构中的每一个相邻的侧壁间隔，之后执行氟注入工艺。

公开(公告)号：US20140238045A1

公开(公告)日：2014-08-28

申请号：US14270941

申请日：2014-05-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Uwe Griebenow ,  Jan Hoentschel ,  Thilo Scheiper ,  Sven Beyer

IPC: H01L23/38

CPC classification number: H01L23/38 ,  G06F1/20 ,  H01L25/0652 ,  H01L25/162 ,  H01L35/32 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of controlling temperature in a semiconductor device that includes a stacked device configuration is disclosed. The method includes providing a Peltier element having a metal-based heat sink formed above a first substrate of the stacked device configuration and a metal-based heat source formed above a second substrate of the stacked device configuration, and establishing a current flow through the Peltier element when the semiconductor device is in a specified operating phase.

Abstract translation: 公开了一种控制包括层叠器件配置的半导体器件中的温度的方法。 该方法包括提供一种珀尔帖元件，其具有形成在层叠器件配置的第一衬底之上的金属基散热器和形成在堆叠器件配置的第二衬底之上的金属基热源，并且建立通过珀尔帖的电流 当半导体器件处于指定的工作阶段时。

公开(公告)号：US20130299891A1

公开(公告)日：2013-11-14

申请号：US13937600

申请日：2013-07-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thilo Scheiper ,  Sven Beyer ,  Uwe Griebenow ,  Jan Hoentschel

IPC: H01L29/788

CPC classification number: H01L29/788 ,  G11C16/0425 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: Storage transistors for flash memory areas in semiconductor devices may be provided on the basis of a self-aligned charge storage region. To this end, a floating spacer element may be provided in some illustrative embodiments, while, in other cases, the charge storage region may be efficiently embedded in the electrode material in a self-aligned manner during a replacement gate approach. Consequently, enhanced bit density may be achieved, since additional sophisticated lithography processes for patterning the charge storage region may no longer be required.

Abstract translation: 可以在自对准电荷存储区域的基础上提供用于半导体器件中的闪存区域的存储晶体管。 为此，可以在一些说明性实施例中提供浮动间隔元件，而在其他情况下，在替换栅极方法期间，电荷存储区域可以以自对准方式有效地嵌入电极材料中。 因此，可以不再需要用于图案化电荷存储区域的附加复杂光刻工艺，可以实现增强的位密度。