公开(公告)号：US10699967B2

公开(公告)日：2020-06-30

申请号：US16021377

申请日：2018-06-28

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Pouya Hashemi ,  Choonghyun Lee

IPC: H01L21/8242 ,  H01L21/8258 ,  H01L27/092 ,  H01L21/225 ,  H01L21/8252 ,  H01L21/8238

Abstract: Embodiments of the invention are directed to a method of fabricating semiconductor devices. A non-limiting example of the method includes forming a first fin in a p-type field effect transistor (PFET) region of a substrate, wherein the first fin includes a first material that includes a first type of semiconductor material at a first concentration level. A second fin is formed in an n-type FET (NFET) region of the substrate, wherein the second fin includes a second semiconductor material that includes a III-V compound. Condensation operations are performed, wherein the condensation operations are configured to increase the first concentration level in at least a portion of the first fin to a targeted final concentration level.

公开(公告)号：US10680083B2

公开(公告)日：2020-06-09

申请号：US16133763

申请日：2018-09-18

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Paul C. Jamison ,  Choonghyun Lee

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762

Abstract: According to an embodiment of the present invention, a semiconductor structure includes a semiconductor substrate and a plurality of fins located on the semiconductor substrate. The plurality of fins each independently includes a bottom fin portion, a top fin portion layer, and an isolated oxide layer located in between the bottom fin portion and the top fin portion layer in the y-direction parallel to the height of the plurality of fins. The isolated oxide layer includes a mixed oxide region located in between oxidized regions in an x-direction perpendicular to the height of the plurality of fins.

公开(公告)号：US10658299B2

公开(公告)日：2020-05-19

申请号：US16412569

申请日：2019-05-15

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Chun Wing Yeung ,  Ruqiang Bao ,  Hemanth Jagannathan

IPC: H01L29/786 ,  H01L23/535 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66

Abstract: A method of forming a semiconductor structure comprises forming a plurality of fins disposed over a top surface of a substrate and forming one or more vertical transport field-effect transistors (VTFETs) from the plurality of fins using a replacement metal gate (RMG) process. A gate surrounding at least one fin of a given one of the VTFETs comprises a gate self-aligned contact (SAC) capping layer disposed over a gate contact metal layer, the gate contact metal layer being disposed adjacent an end of the at least one fin.

公开(公告)号：US20200152769A1

公开(公告)日：2020-05-14

申请号：US16746291

申请日：2020-01-17

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Choonghyun Lee ,  Jingyun Zhang ,  Pouya Hashemi

IPC: H01L29/66 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092

Abstract: VTFET devices having a differential top spacer are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer including NFET and PFET fins; forming bottom source and drains at a base of the NFET/PFET fins; forming bottom spacers on the bottom source and drains; forming gate stacks alongside the NFET/PFET fins that include a same workfunction metal on top of a gate dielectric; annealing the gate stacks which generates oxygen vacancies in the gate dielectric; forming top spacers that include an oxide spacer layer in contact with only the gate stacks alongside the PFET fins, wherein the oxide spacer layer supplies oxygen filling the oxygen vacancies in the gate dielectric only in the gate stacks alongside the PFET fins; and forming top source and drains above the gate stacks at the tops of the NFET/PFET fins. A VTFET device is also provided.

公开(公告)号：US20200152761A1

公开(公告)日：2020-05-14

申请号：US16738383

申请日：2020-01-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Peng Xu ,  Choonghyun Lee ,  Heng Wu

IPC: H01L29/49 ,  H01L21/768 ,  H01L29/66 ,  H01L23/522 ,  H01L29/08

Abstract: A method is presented for reducing parasitic capacitance. The method includes forming a source region and a drain region within a substrate, forming spacers in direct contact with sidewalls of a sacrificial layer, depositing an inter-layer dielectric (ILD) over the source and drain regions, replacing the sacrificial layer with a gate structure, removing the ILD, and depositing a sacrificial dielectric layer. The method further includes removing portions of the sacrificial dielectric layer to expose top surfaces of the source and drain regions, depositing a conductive material over the exposed top surfaces of the source and drain regions, and removing remaining portions of the sacrificial dielectric layer to form air gap spacers between the gate structure and the source and drain regions.

公开(公告)号：US20200105928A1

公开(公告)日：2020-04-02

申请号：US16144196

申请日：2018-09-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Choonghyun Lee ,  Kangguo Cheng ,  Juntao Li ,  Shogo Mochizuki

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/06 ,  H01L29/08 ,  H01L29/04 ,  H01L29/66 ,  H01L29/423

Abstract: A method of forming a semiconductor device that includes forming at least two semiconductor fin structures having sidewalls with {100 } crystalline planes that is present atop a supporting substrate; and epitaxially growing a source/drain region in a lateral direction from the sidewalls of each fin structure. The second source/drain regions have substantially planar sidewalls. A metal wrap around electrode is formed on an upper surface and the substantially planar sidewalls of the source/drain regions. Air gaps are formed between the source/drain regions of the at least two semiconductor fin structures.

公开(公告)号：US10608114B2

公开(公告)日：2020-03-31

申请号：US16009406

申请日：2018-06-15

Applicant: International Business Machines Corporation

Inventor： Injo Ok ,  Choonghyun Lee ,  Soon-Cheon Seo

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/205 ,  H01L29/66 ,  H01L29/16

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and a first source/drain layer in contact with at least the substrate. A vertical channel including indium gallium arsenide or germanium contacts at least the first/source drain layer. A gate structure contacts at least the vertical channel. A second source/drain layer contacts at least inner sidewalls of the vertical channel. The method includes epitaxially growing one or more fin structures comprising gallium arsenide in contact with a portion of a substrate. A separate channel layer comprising indium gallium arsenide or germanium is formed in contact with a respective one of the one or more fin structures.

公开(公告)号：US20200098928A1

公开(公告)日：2020-03-26

申请号：US16692809

申请日：2019-11-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Adra Carr ,  Jingyun Zhang ,  Choonghyun Lee ,  Takashi Ando ,  Pouya Hashemi

IPC: H01L29/786 ,  H01L29/45 ,  H01L29/423 ,  H01L29/06 ,  H01L21/768 ,  H01L29/417 ,  H01L21/285

Abstract: A method of forming a source/drain contact is provided. The method includes forming a sacrificial layer on a source/drain, and depositing an oxidation layer on the sacrificial layer. The method further includes heat treating the oxidation layer and the sacrificial layer to form a modified sacrificial layer. The method further includes forming a protective liner on the modified sacrificial layer, and depositing an interlayer dielectric layer on the protective liner. The method further includes forming a trench in the interlayer dielectric layer that exposes a portion of the protective liner.

公开(公告)号：US10600695B2

公开(公告)日：2020-03-24

申请号：US15986622

申请日：2018-05-22

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Kangguo Cheng ,  Shogo Mochizuki ,  Juntao Li

IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L29/51 ,  H01L21/8234 ,  H01L21/02

Abstract: Techniques for forming VTFET devices with tensile- and compressively-strained channels using dummy stressor materials are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer; forming bottom source and drains at a base of the fins; forming bottom spacers on the bottom source and drains; growing at least one dummy stressor material along sidewalls of the fins above the bottom spacers configured to induce strain in the fins; surrounding the fins with a rigid fill material; removing the at least one dummy stressor material to form gate trenches in the rigid fill material while maintaining the strain in the fins by the rigid fill material; forming replacement gate stacks in the gate trenches; forming top spacers on the replacement gate stacks; and forming top source and drains over the top spacers at tops of the fins. A VTFET device is also provided.

公开(公告)号：US20200091344A1

公开(公告)日：2020-03-19

申请号：US16134543

申请日：2018-09-18

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Choonghyun Lee ,  Pouya Hashemi ,  Takashi Ando ,  Jingyun Zhang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L21/308 ,  H01L21/265

Abstract: A FinFET having an asymmetric threshold voltage distribution is provided by forming a halo ion implantation region in a semiconductor fin, and in close proximity to a source region, of the FinFET. The halo ion implantation region is self-aligned to an outermost sidewall surface of the functional gate structure of the FinFET and it has a higher dopant concentration than the remaining portion of the channel region.