公开(公告)号：US11177437B2

公开(公告)日：2021-11-16

申请号：US16684672

申请日：2019-11-15

Applicant: International Business Machines Corporation

Inventor： Hao Tang ,  Michael Rizzolo ,  Injo Ok ,  Theodorus E. Standaert

IPC: H01L45/00 ,  H01L23/544 ,  H01L27/24

Abstract: An intermediate semiconductor device structure includes a first area including a memory stack area and a second area including an alignment mark area. The intermediate structure includes a metal interconnect arranged on a substrate in the first area and a first electrode layer arranged on the metal interconnect in the first area, and in the second area. The intermediate structure includes an alignment assisting marker arranged in the second area. The intermediate structure includes a dielectric layer and a second electrode layer arranged on the alignment assisting marker in the second area and on the metal interconnect in the first area. The intermediate structure includes a hard mask layer arranged on the second electrode area. The hard mask layer provides a raised area of topography over the alignment assisting marker. The intermediate structure includes a resist arranged on the hard mask layer in the first area.

公开(公告)号：US11158584B2

公开(公告)日：2021-10-26

申请号：US16661383

申请日：2019-10-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael Rizzolo ,  Chih-Chao Yang ,  Lawrence A. Clevenger ,  Benjamin D. Briggs

IPC: H01L23/544 ,  H01L27/22

Abstract: A semiconductor device and method for forming the semiconductor device are described. The method includes recessing a device pad to below a top surface of an interconnect layer and depositing a cap in the recess over the device pad. A topography assist layer is formed over each of at least one alignment mark using a selective deposition process that deposits material on conductive material of the at least one alignment mark selective to the metal nitride of the device pad such that a top surface of the topography assist feature is higher than a top surface of the cap. Device layers are deposited conformally over the interconnect layer such that the topography assist layer causes a topographical feature in a top surface of the deposited device layers, the topographical feature being vertically aligned with the topography assist layer. The device pad is aligned according to the topographical feature.

公开(公告)号：US20210313511A1

公开(公告)日：2021-10-07

申请号：US17353001

申请日：2021-06-21

Applicant: International Business Machines Corporation

Inventor： Michael Rizzolo ,  Oscar van der Straten ,  Alexander Reznicek ,  Oleg Gluschenkov

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A low temperature deposited (400° C. or less) dielectric passivation layer is formed on physically exposed surfaces of a material stack including a multilayered magnetic tunnel junction (MTJ) pillar and a top electrode. A laser anneal is then performed to improve the physical and chemical properties of the low temperature deposited dielectric passivation layer, without negatively impacting the multilayered MTJ pillar.

公开(公告)号：US20210226120A1

公开(公告)日：2021-07-22

申请号：US16748738

申请日：2020-01-21

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Saba Zare ,  Michael Rizzolo ,  Theodorus E. Standaert ,  Daniel C. Edelstein

IPC: H01L43/12

Abstract: Form a metallized layer at a top surface of a semiconductor wafer. The metallized layer includes a bottom contact and a dielectric barrier surrounding the bottom contact. Deposit a memory stack layer onto the metallized layer. The memory stack layer forms a first overspill on a bevel of the wafer. Remove the first overspill from the bevel using a first high-angle ion beam during a cleanup etch.

公开(公告)号：US10957850B2

公开(公告)日：2021-03-23

申请号：US16151401

申请日：2018-10-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashim Dutta ,  Isabel Cristina Chu ,  Son Nguyen ,  Michael Rizzolo ,  John C. Arnold

IPC: H01L29/82 ,  H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L27/22

Abstract: A method for fabricating a semiconductor device includes forming a first encapsulation layer along the device, including forming the first encapsulation layer along a memory device region associated with a memory device, forming an intermediate layer on the first encapsulation layer to enable etch endpoint detection and endpoint-based process control for encapsulation layer etch back, and forming a second encapsulation layer on the intermediate layer.

公开(公告)号：US10957581B2

公开(公告)日：2021-03-23

申请号：US16451269

申请日：2019-06-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Terry A. Spooner ,  Theodorus E. Standaert

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L21/027 ,  H01L21/3105

Abstract: A method of forming via openings that includes forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer that is present on an interlevel dielectric layer. Etching the hardmask layer using a portion of the sidewall spacers and the plurality of mandrels to form a first pillar of hardmask material. The interlevel dielectric layer is etched using the first pillar of hardmask material as a mask to define a first via opening. The plurality of mandrels are removed. The hardmask layer is etched using the spacers to define a second pillar of hardmask material. The interlevel dielectric layer is etched using the second pillar of hardmask material to provide a second via opening.

公开(公告)号：US10943866B2

公开(公告)日：2021-03-09

申请号：US16661416

申请日：2019-10-23

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Michael Rizzolo ,  Christopher J. Penny ,  Huai Huang ,  Lawrence A. Clevenger ,  Hosadurga Shobha

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of trenches in a dielectric layer, wherein the plurality of trenches each comprise a rounded surface, depositing a liner layer on the rounded surface of each of plurality of trenches, and depositing a conductive layer on the liner layer in each of the plurality of trenches, wherein the conductive layer and the liner layer form a plurality of interconnects, and each of the plurality of interconnects has a cylindrical shape.

公开(公告)号：US10833266B2

公开(公告)日：2020-11-10

申请号：US16153195

申请日：2018-10-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Chih-Chao Yang

IPC: H01L45/00 ,  H01L27/24

Abstract: A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a RRAM stack including at least a hardmask having a first layer and a second layer, the second layer being a ruthenium layer, and removing the first layer of dual layer hardmask during a via opening such that the ruthenium layer remains intact to protect the RRAM stack during a damascene process.

公开(公告)号：US10833127B2

公开(公告)日：2020-11-10

申请号：US16294285

申请日：2019-03-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Michael Rizzolo ,  Chih-Chao Yang ,  Lawrence A. Clevenger

IPC: H01L21/44 ,  H01L29/40 ,  H01L27/24 ,  H01L45/00 ,  H01L27/108

Abstract: A method for fabricating a semiconductor device including three-dimensional and planar memory device co-integration includes forming trenches within a horizontal electrode stack to expose portions of a conductive layer, forming vertical electrodes including conductive material within the trenches, forming a planar memory device stack across the device, and patterning the planar memory device stack to form a planar memory device.

公开(公告)号：US10830841B1

公开(公告)日：2020-11-10

申请号：US16445690

申请日：2019-06-19

Applicant: International Business Machines Corporation

Inventor： Nicholas Anthony Lanzillo ,  Benjamin D. Briggs ,  Michael Rizzolo ,  Lawrence A. Clevenger ,  Theodorus E. Standaert ,  James Stathis

IPC: G11C11/16 ,  G01R33/09 ,  H01L27/22

Abstract: A semiconductor device includes a device magnetic tunnel junction (MTJ) and sensor MTJs. A spin polarization of a free layer of the device MTJ is configurable based at least in part on electrical energy supplied to the device MTJ. A spin polarization of a corresponding free layer of each sensor MTJ is configurable based at least in part on a magnetic field created by the spin polarization of the free layer of the device MTJ. A circuit disposed is in electrical communication with the plurality of sensor MTJs and configured to determine the corresponding free layer spin polarizations of each of the sensor MTJs based at least in part on electrical energy supplied to the sensor MTJs by the circuit. The circuit is configured to determine a magnetoresistance of the device MTJ based at least in part on the determined corresponding free layer spin polarizations of the sensor MTJ.