中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

256 records (took 0.027 seconds)

    MATERIAL TEST STRUCTURE
    141.
    发明申请
    MATERIAL TEST STRUCTURE 有权
    材料试验结构

    公开(公告)号：US20150160146A1

    公开(公告)日：2015-06-11

    申请号：US14596406

    申请日：2015-01-14

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Innocenzo Tortorelli ,  Christina Papagianni ,  Gianpaolo Spadini ,  Jong Won Lee

    IPC: G01N27/04

    CPC classification number: G01N27/04 ,  H01L22/34 ,  H01L43/10 ,  H01L45/04 ,  H01L45/06 ,  H01L45/14 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148

    Abstract: Material test structures having cantilever portions and methods of forming the same are described herein. As an example, a method of forming a material test structure includes forming a number of electrode portions in a first dielectric material, forming a second dielectric material on the first dielectric material, wherein the second dielectric material includes a first cantilever portion and a second cantilever portion, and forming a test material on the number of electrode portions, the first dielectric material, and the second dielectric material.

    Abstract translation: 本文描述了具有悬臂部分的材料测试结构及其形成方法。 作为示例，形成材料测试结构的方法包括在第一介电材料中形成多个电极部分，在第一电介质材料上形成第二电介质材料，其中第二电介质材料包括第一悬臂部分和第二悬臂 并且在电极部分，第一介电材料和第二介电材料的数量上形成测试材料。

    Analog storage using memory device
    144.
    发明授权
    Analog storage using memory device 有权

    公开(公告)号：US12080365B2

    公开(公告)日：2024-09-03

    申请号：US17048669

    申请日：2020-01-28

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Innocenzo Tortorelli

    IPC: G11C27/00 ,  G06N3/065 ,  G06N3/08

    CPC classification number: G11C27/005 ,  G06N3/065 ,  G06N3/08

    Abstract: Methods, systems, and devices for analog storing information are described herein. Such methods, systems and devices are suitable for synaptic weight storage in electronic neuro-biological mimicking architectures. A memory device may include a plurality of memory cells each respective memory cell in the plurality of memory cells with a respective programming sensitivity different from the respective programming sensitivity of other memory cells in the plurality. Memory cells may be provided on different decks of a multi-deck memory array. A storage element material of a respective memory cell may have a thickness and/or a composition different from another thickness or composition of a respective storage element material of another respective memory cell on a different deck in the multi-deck memory array. The memory device may further include reading circuitry configured to analogically read respective information programmed in the respective memory cells and to provide an output based on a combination of the respective information analogically read from the respective memory cells.

    CROSS-POINT PILLAR ARCHITECTURE FOR MEMORY ARRAYS
    146.
    发明公开
    CROSS-POINT PILLAR ARCHITECTURE FOR MEMORY ARRAYS 审中-公开

    公开(公告)号：US20240221829A1

    公开(公告)日：2024-07-04

    申请号：US18409992

    申请日：2024-01-11

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer ,  Mattia Robustelli ,  Alessandro Sebastiani

    IPC: G11C13/00

    CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71

    Abstract: Methods, systems, and devices for a cross-point pillar architecture for memory arrays are described. Multiple selector devices may be configured to access or activate a pillar within a memory array, where the selector devices may each be or include a chalcogenide material. A pillar access line may be coupled with multiple selector devices, where each selector device may correspond to a pillar associated with the pillar access line. Pillar access lines on top and bottom of the pillars of the memory array may be aligned in a square or rectangle formation, or in a hexagonal formation. Pillars and corresponding selector devices on top and bottom of the pillars may be located at overlapping portions of the pillar access lines, thereby forming a cross point architecture for pillar selection or activation. The selector devices may act in pairs to select or activate a pillar upon application of a respective selection voltage.

    Pulse based multi-level cell programming
    147.
    发明授权
    Pulse based multi-level cell programming 有权

    公开(公告)号：US11984191B2

    公开(公告)日：2024-05-14

    申请号：US17740069

    申请日：2022-05-09

    Applicant: Micron Technology, Inc.

    Inventor： Hernan A. Castro ,  Mattia Boniardi ,  Innocenzo Tortorelli

    IPC: G11C8/00 ,  G11C7/10 ,  G11C16/34

    CPC classification number: G11C7/1039 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093 ,  G11C16/3404

    Abstract: Methods, systems, and devices for pulse based multi-level cell programming are described. A memory device may identify an intermediate logic state to store to a multi-level memory cell capable of storing three or more logic states. The memory device may apply a first pulse with a first polarity to the memory cell to store a SET or RESET state to the memory cell based on identifying the intermediate logic state. As such, the memory device may identify a threshold voltage of the memory cell that stores the SET or RESET state. The memory device may apply a quantity of pulses to the memory cell to store the identified intermediate logic state based on identifying the threshold voltage of the memory cell that stores the SET or RESET state. In some examples, the quantity of pulses may have a second polarity different than the first polarity.

    MEMORY AND STORAGE ON A SINGLE CHIP
    148.
    发明公开
    MEMORY AND STORAGE ON A SINGLE CHIP 审中-公开

    公开(公告)号：US20240130143A1

    公开(公告)日：2024-04-18

    申请号：US17968744

    申请日：2022-10-18

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli ,  Agostino Pirovano ,  Matteo Impalà ,  Mattia Robustelli ,  Fabio Pellizzer

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2481 ,  H01L45/06 ,  H01L45/143 ,  H01L45/1683

    Abstract: A single memory chip including both memory and storage capabilities on the single chip and accompanying process for forming a memory array including both capabilities is disclosed. In particular, the single chip may incorporate the use of two different chalcogenide materials deposited thereon to implement the memory and storage capabilities. Chalcogenide materials provide flexibility on cell performance, such as by changing the chalcogenide material composition. For the single memory chip, one type of chalcogenide material may be utilized to create memory cells and another type of chalcogenide material may be utilized to create storage cells. The process for forming the memory array includes forming first and second openings in a starting structure and performing a series of etching and deposition steps on the structure to form the memory and storage cells using the two different chalcogenide compositions. The memory and storage cells are independently addressable via wordline and bitline selection.

    TIMING FOR OPERATIONS IN MEMORY DEVICE STORING BITS IN MEMORY CELL PAIRS
    149.
    发明公开
    TIMING FOR OPERATIONS IN MEMORY DEVICE STORING BITS IN MEMORY CELL PAIRS 审中-公开

    公开(公告)号：US20230395135A1

    公开(公告)日：2023-12-07

    申请号：US17864046

    申请日：2022-07-13

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi ,  Efrem Bolandrina ,  Innocenzo Tortorelli

    IPC: G11C11/4096 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4076

    CPC classification number: G11C11/4096 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4076

    Abstract: Systems, methods, and apparatus related to memory devices (e.g., storage class memory). In one approach, a memory device has a memory array including memory cells arranged as differential memory cell pairs, with each pair storing a single logical bit. The memory device has a controller that receives a command from a host to initiate a read operation. The memory cell pair is selected using bitlines and a common wordline. A partition of the memory array is accessed to read the data stored by the memory cell pair, and then store the read data in a latch for sending to the host. In response to accessing the partition, a counter is incremented. The controller statistically determines whether to perform a refresh operation for the partition based on comparing the current value of the counter to a value previously generated by a random number generator.

    ASYMMETRIC MEMORY CELL DESIGN
    150.
    发明公开
    ASYMMETRIC MEMORY CELL DESIGN 审中-公开

    公开(公告)号：US20230354619A1

    公开(公告)日：2023-11-02

    申请号：US17818923

    申请日：2022-08-10

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Robustelli ,  Innocenzo Tortorelli

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/249 ,  H01L45/06 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/1683

    Abstract: Methods, systems, and devices for asymmetric memory cell design are described. A memory device may implement a programming scheme that uses low programming pulses based on an asymmetric memory cell design. For example, the asymmetric memory cells may have electrodes with different contact areas (e.g., widths) and may accordingly be biased to a desired polarity (e.g., negative biased or positive biased) for programming operations. That is, the asymmetric memory cell design may enable an asymmetric read window budget. For example, an asymmetric memory cell may be polarity biased, supporting programming operations for logic states based on the polarity bias.

Patent Agency Ranking